AT27LV256A-55TU

AT27LV256A-55TU Datasheet


• Pin Compatible with JEDEC Standard AT27C256R<br>• Low-power CMOS Operation

Part Datasheet
AT27LV256A-55TU AT27LV256A-55TU AT27LV256A-55TU (pdf)
Related Parts Information
AT27LV256A-90TU AT27LV256A-90TU AT27LV256A-90TU
AT27LV256A-55JU AT27LV256A-55JU AT27LV256A-55JU
AT27LV256A-55RU AT27LV256A-55RU AT27LV256A-55RU
AT27LV256A-90RU AT27LV256A-90RU AT27LV256A-90RU
PDF Datasheet Preview
• Fast Read Access Time 55 ns
• Dual Voltage Range Operation

Low-voltage Power Supply Range, 3.0V to 3.6V or Standard 5V ± 10% Supply Range
• Pin Compatible with JEDEC Standard AT27C256R
• Low-power CMOS Operation
20 µA Max Less than 1 µA Typical Standby for VCC = 3.6V 29 mW Max Active at 5 MHz for VCC = 3.6V
• JEDEC Standard Packages 32-lead PLCC 28-lead SOIC 28-lead TSOP
• High-reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity
• Rapid Programming Algorithm 100 µs/Byte Typical
• CMOS and TTL Compatible Inputs and Outputs JEDEC Standard for LVTTL
• Integrated Product Identification Code
• Industrial Temperature Range
• Green Pb/Halide-free Packaging Option
256K 32K x 8 Low-voltage OTP EPROM

AT27LV256A

The AT27LV256A is a high-performance, low-power, low-voltage 262,144-bit onetime programmable read-only memory OTP EPROM organized as 32K by 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode operation, making it ideal for fast, portable systems using battery power.

Atmel’s innovative design techniques provide fast speeds that rival 5V parts while keeping the low power consumption of a 3.3V supply. At VCC = 3.0V, any byte can be accessed in less than 55 ns. With a typical power dissipation of only 18 mW at 5 MHz and VCC = 3.3V, the AT27LV256A consumes less than one fifth the power of a standard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3.3V.

The AT27LV256A is available in industry-standard JEDEC-approved one-time programmable OTP plastic PLCC, SOIC and TSOP packages. All devices feature two-line control CE, OE to give designers the flexibility to prevent bus contention.

The AT27LV256A operating with VCC at 3.0V produces TTL level outputs that are compatible with standard TTL logic devices operating at VCC = 5.0V. The device is also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable in both 3-volt and 5-volt hosts.

Atmel’s AT27LV256A has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. The AT27LV256A programs exactly the same way as a standard 5V AT27C256R and uses the same programming equipment.

AT27LV256A

Pin Configurations

Pin Name A0 - A14 O0 - O7 CE OE NC

Function Addresses Outputs Chip Enable Output Enable No Connect
28-lead SOIC Top View

VPP 1 A12 2

A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 O0 11 O1 12 O2 13 GND 14
28 VCC 27 A14 26 A13 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 O7 18 O6 17 O5 16 O4 15 O3
28-lead TSOP Type 1 Top View

OE 22 A11 23

A9 24 A8 25 A13 26 A14 27 VCC 28 VPP 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7
21 A10 20 CE 19 O7 18 O6 17 O5 16 O4 15 O3 14 GND 13 O2 12 O1 11 O0 10 A0
9 A1 8 A2
32-lead PLCC Top View
4 A7 3 A12 2 VPP 1 NC 32 VCC 31 A14 30 A13

A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 O0 13
29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 O7 21 O6

O1 14 O2 15 GND 16 NC 17 O3 18 O4 19 O5 20

Note PLCC Package Pins 1 and 17 are Don’t Connect.

AT27LV256A

System Considerations

Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C

Storage Temperature -65°C to +125°C

Voltage on Any Pin with Respect to Ground to +7.0V 1

Voltage on A9 with Respect to Ground to +14.0V 1

VPP Supply Voltage with Respect to Ground to +14.0V 1
*NOTICE:
Ordering Information

Standard Package
tACC

ICC mA

Active

Standby
Ordering Code AT27LV256A-55JI AT27LV256A-55RI AT27LV256A-55TI AT27LV256A-90JI AT27LV256A-90RI AT27LV256A-90TI

Package
32J 28R 1 28T
32J 28R 1 28T

Note:

Not recommended for new designs. Use Green package option.

Green Package Option Pb/Halide-free
tACC

ICC mA

Active

Standby
Ordering Code

AT27LV256A-55JU

AT27LV256A-55RU

AT27LV256A-55TU

AT27LV256A-90JU

AT27LV256A-90RU

AT27LV256A-90TU

Note The 28-pin SOIC package is not recommended for new designs.

Package
32J 28R 1 28T
32J 28R 1 28T

AT27LV256A

Operation Range Industrial
-40° C to 85° C Industrial
-40° C to 85° C

Operation Range Industrial
-40° C to 85° C Industrial
-40° C to 85° C

Package Type
32-lead, Plastic J-leaded Chip Carrier PLCC
28-lead, Wide, Plastic Gull Wing Small Outline SOIC
28-lead, Thin Small Outline Package TSOP

Packaging Information
32J PLCC

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
12 AT27LV256A
28R SOIC

AT27LV256A

PIN 1 e
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Datasheet ID: AT27LV256A-55TU 518955