AT49F040-90JI

AT49F040-90JI Datasheet

The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA.

Part	Datasheet
AT49F040-90JI	AT49F040-90JI (pdf)

Related Parts	Information
AT49F040-70JI	AT49F040-70JI
AT49F040-90JC	AT49F040-90JC
AT49F040-90PC	AT49F040-90PC
AT49F040-90PI	AT49F040-90PI
AT49F040-90TI	AT49F040-90TI
AT49F040-12TI	AT49F040-12TI
AT49F040-90TC	AT49F040-90TC
AT49F040-15JI	AT49F040-15JI
AT49F040-12TC	AT49F040-12TC
AT49F040-12PI	AT49F040-12PI
AT49F040-12PC	AT49F040-12PC
AT49F040-12JI	AT49F040-12JI
AT49F040-12JC	AT49F040-12JC
AT49F040-70JC	AT49F040-70JC
AT49F040-70TC	AT49F040-70TC
AT49F040-70PI	AT49F040-70PI
AT49F040-70PC	AT49F040-70PC
AT49F040-70TI	AT49F040-70TI

PDF Datasheet Preview
• Single-voltage Operation 5V Read 5V Reprogramming • Fast Read Access Time 55 ns • Internal Program Control and Timer • 16-Kbyte Boot Block with Lockout • Fast Erase Cycle Time 10 seconds • Byte-by-byte Programming 50 µs/Byte • Hardware Data Protection • DATA Polling for End of Program Detection • Low Power Dissipation 50 mA Active Current 100 µA CMOS Standby Current • Typical 10,000 Write Cycles The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The device contains a user-enabled “boot block” protection feature. The AT49F040 locates the boot block at lowest order addresses “bottom boot” . continued 4-megabit 512K x 8 5-volt Only Flash Memory AT49F040 Pin Configurations Pin Name A0 - A18 CE OE WE I/O0 - I/O7 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs TSOP Top View Type 1 A11 1 A9 2 A8 3 A13 4 A14 5 A17 6 WE 7 VCC 8 A18 9 A16 10 A15 11 A12 12 A7 13 A6 14 A5 15 A4 16 32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3 I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20 DIP Top View A18 1 A16 2 A15 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16 32 VCC 31 WE 30 A17 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 PLCC Top View 4 A12 3 A15 2 A16 1 A18 32 VCC 31 WE 30 A17 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 To allow for simple in-system reprogrammability, the AT49F040 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F040 is performed by erasing the entire 4 megabits of memory and then programming on a byte-by-byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. Block Diagram VCC GND OE WE CE ADDRESS INPUTS OE, CE, AND WE LOGIC Y DECODER X DECODER DATA INPUTS/OUTPUTS I/O7 - I/O0 DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY 496K BYTES OPTIONAL BOOT BLOCK 16K BYTES 7FFFFH AT49F040 Ordering Information tACC ICC mA Active Standby Ordering Code AT49F040-55JC AT49F040-55PC AT49F040-55TC AT49F040-55JI AT49F040-55PI AT49F040-55TI AT49F040-70JC AT49F040-70PC AT49F040-70TC AT49F040-70JI AT49F040-70PI AT49F040-70TI AT49F040-90JC AT49F040-90PC AT49F040-90TC AT49F040-90JI AT49F040-90PI AT49F040-90TI AT49F040-12JC AT49F040-12PC AT49F040-12TC AT49F040-12JI AT49F040-12PI AT49F040-12TI AT49F040 Package 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C 32J 32P6 32T Package Type 32-lead, Plastic, J-leaded Chip Carrier Package PLCC 32-lead, Wide, Plastic Dual Inline Package PDIP 32-lead, Thin Small Outline Package TSOP Packaging Information 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters JEDEC STANDARD MS-016 AE X PIN NO. 1 IDENTIFY AT CONTACT POINTS X MAX 3X 32T, 32-lead, Plastic Thin Small Outline Package TSOP Dimensions in Millimeters and Inches * JEDEC OUTLINE MO-142 BA INDEX MARK 32P6, 32-lead, Wide, Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters PIN 1 SEATING PLANE

PDF Datasheet Preview

• Single-voltage Operation 5V Read 5V Reprogramming
• Fast Read Access Time 55 ns
• Internal Program Control and Timer
• 16-Kbyte Boot Block with Lockout
• Fast Erase Cycle Time 10 seconds
• Byte-by-byte Programming 50 µs/Byte
• Hardware Data Protection
• DATA Polling for End of Program Detection
• Low Power Dissipation
50 mA Active Current 100 µA CMOS Standby Current
• Typical 10,000 Write Cycles

The AT49F040 is a 5-volt-only in-system Flash Memory. Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA.

The device contains a user-enabled “boot block” protection feature. The AT49F040 locates the boot block at lowest order addresses “bottom boot” .
continued
4-megabit 512K x 8 5-volt Only Flash Memory

AT49F040

Pin Configurations

Pin Name A0 - A18 CE OE WE I/O0 - I/O7

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs

TSOP Top View Type 1

A11 1 A9 2 A8 3

A13 4 A14 5 A17 6 WE 7 VCC 8 A18 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

DIP Top View

A18 1 A16 2 A15 3 A12 4

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16
32 VCC 31 WE 30 A17 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3

PLCC Top View
4 A12 3 A15 2 A16 1 A18 32 VCC 31 WE 30 A17

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

To allow for simple in-system reprogrammability, the AT49F040 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F040 is performed by erasing the entire 4 megabits of memory and then programming on a byte-by-byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.

Block Diagram

VCC GND

OE WE CE

ADDRESS INPUTS

OE, CE, AND WE LOGIC

Y DECODER X DECODER

DATA INPUTS/OUTPUTS I/O7 - I/O0

DATA LATCH

INPUT/OUTPUT BUFFERS

Y-GATING

MAIN MEMORY 496K BYTES

OPTIONAL BOOT BLOCK 16K BYTES
7FFFFH
AT49F040 Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT49F040-55JC AT49F040-55PC AT49F040-55TC

AT49F040-55JI AT49F040-55PI AT49F040-55TI

AT49F040-70JC AT49F040-70PC AT49F040-70TC

AT49F040-70JI AT49F040-70PI AT49F040-70TI

AT49F040-90JC AT49F040-90PC AT49F040-90TC

AT49F040-90JI AT49F040-90PI AT49F040-90TI

AT49F040-12JC AT49F040-12PC AT49F040-12TC

AT49F040-12JI AT49F040-12PI AT49F040-12TI

AT49F040

Package
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T
32J 32P6 32T

Operation Range Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C

Commercial 0° to 70°C

Industrial -40° to 85°C
32J 32P6 32T

Package Type 32-lead, Plastic, J-leaded Chip Carrier Package PLCC 32-lead, Wide, Plastic Dual Inline Package PDIP 32-lead, Thin Small Outline Package TSOP

Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

JEDEC STANDARD MS-016 AE

X PIN NO. 1 IDENTIFY

AT CONTACT POINTS

X MAX 3X
32T, 32-lead, Plastic Thin Small Outline Package TSOP Dimensions in Millimeters and Inches *

JEDEC OUTLINE MO-142 BA

INDEX MARK
32P6, 32-lead, Wide, Plastic Dual Inline Package PDIP Dimensions in Inches and Millimeters

PIN 1

SEATING PLANE

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT49F040-90JI Datasheet file may be downloaded here without warranties.

Datasheet ID: AT49F040-90JI 518691