AT91CAP7E-NA-ZJ

AT91CAP7E-NA-ZJ Datasheet

AT91CAP7E

Part	Datasheet
AT91CAP7E-NA-ZJ	AT91CAP7E-NA-ZJ (pdf)

PDF Datasheet Preview
• Incorporates the Processor 72 MIPS at 80MHz EmbeddedICE In-circuit Emulation, Debug Communication Channel Support • Additional Embedded Memories One 256 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Matrix Speed Configured in blocks of 96 KB and 64 KB with separate AHB slaves • External Bus Interface EBI Supports SDRAM, Static Memory, NAND and • USB Full Speed 12 Mbits per second Device Port On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM • FPGA Interface High Connectivity for up to 2 AHB Masters and 4 dedicated/16 muxed Slaves • 10-bit Analog to Digital Converter ADC Up to 8 multiplexed channels 440 kSample / s • Bus Matrix Four-layer, 32-bit Matrix • Fully-featured System Controller, including Reset Controller, Shut Down Controller Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes Clock Generator Advanced Power Management Controller APMC Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-Time Timer • Boot Mode Select Option and Remap Command • Reset Controller Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control • Shut Down Controller Programmable Shutdown Pin Control and Wake-up Circuitry • Clock Generator CKGR 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock Internal 32kHz RC oscillator for fast start-up 8 to 16 MHz On-chip Oscillator, 50 to 100 MHz PLL, and 80 to 240 MHz PLL • Advanced Power Management Controller APMC Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Output Signals • Advanced Interrupt Controller AIC Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Two External Interrupt Sources and one Fast Interrupt Source, Spurious interrupt protected • Debug Unit DBGU 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Customizable Microcontroller AT91CAP7E • Periodic Interval Timer PIT 20-bit interval Timer plus 12-bit interval Counter • Watchdog Timer WDT Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock • Real-Time Timer RTT 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler • Two 32-bit Parallel Input/Output Controllers PIOA and PIOB 32 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os each Input Change Interrupt Capability on Each I/O Line Individually Programmable Open-drain, Pull-up Resistor, Bus Holder and Synchronous Output • 22 Peripheral DMA Controller Channels PDC • Two Universal Synchronous/Asynchronous Receiver Transmitters USART Individual Baud Rate Generator, Infrared Modulation/Demodulation, Manchester Encoding/Decoding • Master/Slave Serial Peripheral Interface SPI 8- to 16-bit Programmable Data Length, External Peripheral Chip Select Synchronous Communications at up to 80Mbits/sec • One Three-channel 16-bit Timer/Counters TC Three External Clock Inputs, Two multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • IEEE JTAG Boundary Scan on All Digital Pins • Required Power Supplies • 1.08V to 1.32V for VDDCORE and VDDBU • 1.08V to 1.32V for VDDOSC, VDDOSC32, and VDDPLLB • 3.0V to 3.6V for VDDPLLA and VDDIO • 3.0V to 3.6V for AVDD ADC • Package Options 144 LQFP, 176 LQFP, 208 PQFP, 144 LFBGA, 176TFBGA, 208 TFBGA, 225 LFBGA The AT91CAP7E semi-custom System on a Chip SoC is a microcontroller with a special interface that allows logic in an external FPGA to be mapped directly onto its internal Amba High-speed Bus AHB . This FPGA interface includes multiple master and slave channels providing much greater bus bandwidth for data passing between the microcontroller and an FPGA than traditional interface methods using general purpose I/O or external memory interfaces. The AT91CAP7E includes an ARM7TDMI core with the AHB, on-chip ROM, SRAM, a full-featured system controller, and various general-purpose peripherals accessible via the Amba Peripheral Bus APB . It is implemented in a 130 nm CMOS 1.2V process and supports 3.3V I/O. The AT91CAP7E is built upon Atmel’s AT91CAP7S customizablemicrocontroller with up to 450 Kgates of metal programmable MP logic. The FPGA Interface is implemented inthe MP block and makes use of MP I/O’s available on the AT91CAP7S giving customers not only an efficient, powerful FPGA interface on a standard microcontroller, but also an excellent platform for emulating their own AT91CAP7S-based designs. 2 AT91CAP7E Block Diagram Figure AT91CAP7E Block Diagram JTAGSEL TDI TDO TMS TCK NTRST TST FIQ IRQ0-IRQ1 DRXD DTXD PCK0-PCK3 PLLRCA XIN XOUT XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 NPCS00 NPCS01 NPCS02 NPCS03 MISO0 MOSI0 SPCK0 AT91CAP7E Ordering Information Table AT91CAP7E Ordering Information Ordering Code Package AT91CAP7E BGA225 Package Type RoHS Compliant AT91CAP7E Temperature Operating Range Industrial -40°C to 85°C 502 AT91CAP7E Date 10/2008 Comments Initial document release. AT91CAP7E 504 AT91CAP7E AT91CAP7E Table of Contents 1 Description 2 2 Block Diagram 3 3 Signal Description 4 4 Package and Pinout 11 4.1Mechanical Overview of the 225-ball LFBGA Package 4.2225-ball LFBGA Package Pinout 5 Power Considerations 14 5.1Power Supplies 5.2Power Consumption 6 I/O Line Considerations 15 6.1JTAG Port Pins 6.2Test Pin 6.3Reset Pins 6.4PIO Controllers 6.5Shut Down Logic pins 7 Processor and Architecture 16 7.1ARM7TDMI Processor 7.2Debug and Test Features 7.3Bus Matrix 7.4.1Matrix Masters 17 7.5.2Matrix Slaves 17 7.6Peripheral DMA Controller 8 Memories 18 8.1Embedded Memories 8.2Memory Mapping 8.3Internal Memory Mapping 8.4.1Internal 160-kBytes Fast SRAM 19 8.5.2Boot Memory 19 8.6Boot Program 8.7External Memories Mapping 8.8External Bus Interface 8.9.1Static Memory Controller 20 8.10.2SDRAM Controller 20 9 System Controller 22 9.1System Controller Block Diagram 9.2System Controller Mapping 9.3Reset Controller 9.4Shut Down Controller 9.5Clock Generator 9.6Power Management Controller 9.7Periodic Interval Timer 9.8Watchdog Timer 9.9Real-Time Timer 9.10General-Purpose Backed-up Registers 9.11Backup Power Switch 9.12Advanced Interrupt Controller 9.13Debug Unit 9.14Chip Identification 9.15PIO Controllers 9.16User Interface 9.17.1Special System Controller Register Mapping 30 9.18.2Oscillator Mode Register 30 9.19.3General Purpose Backup Register 31 10 Peripherals 32 10.1Peripheral Mapping 10.2Peripheral Identifiers 10.3Peripheral Interrupts and Clock Control 10.4.1System Interrupt 35 10.5.2External Interrupts 35 10.6.3Timer Counter Interrupts 35 10.7Peripherals Signals Multiplexing on I/O Lines 10.8.1PIO Controller A Multiplexing 36 10.9.2PIO Controller B Multiplexing 37 10.10.3Resource Multiplexing 37 10.11Embedded Peripherals Overview 10.12.1Serial Peripheral Interface 38 10.13.2USART 38 10.14.3Timer Counter 39 10.15.4USB Device Port 39 10.16.5Analog to Digital Converter 39 11 FPGA Interface FPIF 41 11.1Description 506 AT91CAP7E AT91CAP7E 11.2System Requirements and Integration 11.3Functional Description 35 AT91CAP7E Ordering Information 501 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support Sales Contact Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2007 Atmel Corporation. All rights reserved. logo and combinations thereof, and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. and others are registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others.

PDF Datasheet Preview

• Incorporates the Processor 72 MIPS at 80MHz EmbeddedICE In-circuit Emulation, Debug Communication Channel Support
• Additional Embedded Memories One 256 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Matrix Speed Configured in blocks of 96 KB and 64 KB with separate AHB slaves
• External Bus Interface EBI Supports SDRAM, Static Memory, NAND and
• USB Full Speed 12 Mbits per second Device Port On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
• FPGA Interface High Connectivity for up to 2 AHB Masters and 4 dedicated/16 muxed Slaves
• 10-bit Analog to Digital Converter ADC Up to 8 multiplexed channels 440 kSample / s
• Bus Matrix Four-layer, 32-bit Matrix
• Fully-featured System Controller, including Reset Controller, Shut Down Controller Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes Clock Generator Advanced Power Management Controller APMC Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-Time Timer
• Boot Mode Select Option and Remap Command
• Reset Controller

Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
• Shut Down Controller Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator CKGR 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock Internal 32kHz RC oscillator for fast start-up 8 to 16 MHz On-chip Oscillator, 50 to 100 MHz PLL, and 80 to 240 MHz PLL
• Advanced Power Management Controller APMC Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Four Programmable External Clock Output Signals
• Advanced Interrupt Controller AIC Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Two External Interrupt Sources and one Fast Interrupt Source, Spurious interrupt protected
• Debug Unit DBGU 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention

Customizable Microcontroller

AT91CAP7E
• Periodic Interval Timer PIT 20-bit interval Timer plus 12-bit interval Counter
• Watchdog Timer WDT Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-Time Timer RTT 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• Two 32-bit Parallel Input/Output Controllers PIOA and PIOB 32 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os each Input Change Interrupt Capability on Each I/O Line Individually Programmable Open-drain, Pull-up Resistor, Bus Holder and Synchronous Output
• 22 Peripheral DMA Controller Channels PDC
• Two Universal Synchronous/Asynchronous Receiver Transmitters USART

Individual Baud Rate Generator, Infrared Modulation/Demodulation, Manchester Encoding/Decoding
• Master/Slave Serial Peripheral Interface SPI
8- to 16-bit Programmable Data Length, External Peripheral Chip Select Synchronous Communications at up to 80Mbits/sec
• One Three-channel 16-bit Timer/Counters TC Three External Clock Inputs, Two multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• IEEE JTAG Boundary Scan on All Digital Pins
• Required Power Supplies
• 1.08V to 1.32V for VDDCORE and VDDBU
• 1.08V to 1.32V for VDDOSC, VDDOSC32, and VDDPLLB
• 3.0V to 3.6V for VDDPLLA and VDDIO
• 3.0V to 3.6V for AVDD ADC
• Package Options 144 LQFP, 176 LQFP, 208 PQFP, 144 LFBGA, 176TFBGA, 208 TFBGA, 225 LFBGA

The AT91CAP7E semi-custom System on a Chip SoC is a microcontroller with a special interface that allows logic in an external FPGA to be mapped directly onto its internal Amba High-speed Bus AHB . This FPGA interface includes multiple master and slave channels providing much greater bus bandwidth for data passing between the microcontroller and an FPGA than traditional interface methods using general purpose I/O or external memory interfaces. The AT91CAP7E includes an ARM7TDMI core with the AHB, on-chip ROM, SRAM, a full-featured system controller, and various general-purpose peripherals accessible via the Amba Peripheral Bus APB . It is implemented in a 130 nm CMOS 1.2V process and supports 3.3V I/O.

The AT91CAP7E is built upon Atmel’s AT91CAP7S customizablemicrocontroller with up to 450 Kgates of metal programmable MP logic. The FPGA Interface is implemented inthe MP block and makes use of MP I/O’s available on the AT91CAP7S giving customers not only an efficient, powerful FPGA interface on a standard microcontroller, but also an excellent platform for emulating their own AT91CAP7S-based designs.
2 AT91CAP7E

Block Diagram

Figure AT91CAP7E Block Diagram

JTAGSEL TDI TDO TMS TCK

NTRST

TST FIQ IRQ0-IRQ1 DRXD DTXD PCK0-PCK3

PLLRCA

XIN XOUT

XIN32 XOUT32

SHDN WKUP

VDDBU GNDBU

VDDCORE NRST

RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1

NPCS00 NPCS01 NPCS02 NPCS03

MISO0 MOSI0 SPCK0
AT91CAP7E Ordering Information
Table AT91CAP7E Ordering Information
Ordering Code

Package

AT91CAP7E

BGA225

Package Type RoHS Compliant

AT91CAP7E

Temperature Operating Range Industrial
-40°C to 85°C
502 AT91CAP7E

Date 10/2008

Comments Initial document release.

AT91CAP7E
504 AT91CAP7E

AT91CAP7E

Table of Contents
1 Description 2
2 Block Diagram 3
3 Signal Description 4
4 Package and Pinout 11
4.1Mechanical Overview of the 225-ball LFBGA Package 4.2225-ball LFBGA Package Pinout
5 Power Considerations 14
5.1Power Supplies 5.2Power Consumption
6 I/O Line Considerations 15
6.1JTAG Port Pins 6.2Test Pin 6.3Reset Pins 6.4PIO Controllers 6.5Shut Down Logic pins
7 Processor and Architecture 16
7.1ARM7TDMI Processor 7.2Debug and Test Features 7.3Bus Matrix
7.4.1Matrix Masters 17 7.5.2Matrix Slaves 17 7.6Peripheral DMA Controller
8 Memories 18
8.1Embedded Memories 8.2Memory Mapping 8.3Internal Memory Mapping
8.4.1Internal 160-kBytes Fast SRAM 19 8.5.2Boot Memory 19 8.6Boot Program 8.7External Memories Mapping 8.8External Bus Interface 8.9.1Static Memory Controller 20 8.10.2SDRAM Controller 20
9 System Controller 22
9.1System Controller Block Diagram 9.2System Controller Mapping 9.3Reset Controller 9.4Shut Down Controller 9.5Clock Generator 9.6Power Management Controller 9.7Periodic Interval Timer 9.8Watchdog Timer 9.9Real-Time Timer 9.10General-Purpose Backed-up Registers 9.11Backup Power Switch 9.12Advanced Interrupt Controller 9.13Debug Unit 9.14Chip Identification 9.15PIO Controllers 9.16User Interface
9.17.1Special System Controller Register Mapping 30 9.18.2Oscillator Mode Register 30 9.19.3General Purpose Backup Register 31
10 Peripherals 32
10.1Peripheral Mapping 10.2Peripheral Identifiers 10.3Peripheral Interrupts and Clock Control
10.4.1System Interrupt 35 10.5.2External Interrupts 35 10.6.3Timer Counter Interrupts 35 10.7Peripherals Signals Multiplexing on I/O Lines 10.8.1PIO Controller A Multiplexing 36 10.9.2PIO Controller B Multiplexing 37 10.10.3Resource Multiplexing 37 10.11Embedded Peripherals Overview 10.12.1Serial Peripheral Interface 38 10.13.2USART 38 10.14.3Timer Counter 39 10.15.4USB Device Port 39 10.16.5Analog to Digital Converter 39
11 FPGA Interface FPIF 41
11.1Description
506 AT91CAP7E

AT91CAP7E
11.2System Requirements and Integration 11.3Functional Description
35 AT91CAP7E Ordering Information 501

Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Product Contact

Web Site

Literature Requests

Technical Support

Sales Contact

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2007 Atmel Corporation. All rights reserved. logo and combinations thereof, and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. and others are registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others.

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Datasheet ID: AT91CAP7E-NA-ZJ 519108