CY7C68013-56PVC

CY7C68013-56PVC Datasheet

CY7C68013

Part	Datasheet
CY7C68013-56PVC	CY7C68013-56PVC (pdf)

Related Parts	Information
CY7C68013-100AC	CY7C68013-100AC

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CY7C68013 CY7C68013 EZ-USB FX2 USB Microcontroller High-speed USB Peripheral Controller 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C68013 TABLE OF CONTENTS EZ-USB FX2 FEATURES 6 APPLICATIONS 7 FUNCTIONAL OVERVIEW 7 USB Signaling Speed 7 8051 Microprocessor 7 I2C-compatible Bus 8 Buses 8 USB Boot Methods 9 ReNumeration 9 Bus Powered Applications 9 Interrupt System 10 Reset and Wakeup 11 Program/Data RAM 11 Register Addresses 14 Endpoint RAM 14 External FIFO interface 16 GPIF 16 USB Uploads and Downloads 17 Autopointer Access 17 I2C-compatible Controller 17 PIN ASSIGNMENTS 18 CY7C68013 Pin Descriptions 24 REGISTER SUMMARY 31 ABSOLUTE MAXIMUM RATINGS 37 OPERATING CONDITIONS 37 DC CHARACTERISTICS 37 USB Transceiver 37 AC ELECTRICAL CHARACTERISTICS 38 USB Transceiver 38 Program Memory Read 38 Data Memory Read 39 Data Memory Write 40 GPIF Synchronous Signals 41 Slave FIFO Synchronous Read 42 Slave FIFO Asynchronous Read 43 Slave FIFO Synchronous Write 43 Slave FIFO Asynchronous Write 44 Slave FIFO Synchronous Packet End Strobe 44 Slave FIFO Asynchronous Packet End Strobe 45 Slave FIFO Output Enable 45 Slave FIFO Address to Flags/Data 45 Slave FIFO Synchronous Address 46 Slave FIFO Asynchronous Address 46 Page 2 of 52 CY7C68013 ORDERING INFORMATION 46 PACKAGE DIAGRAMS 47 PCB LAYOUT RECOMMENDATIONS 50 QUAD FLAT PACKAGE NO LEADS QFN PACKAGE DESIGN NOTES 50 Page 3 of 52 CY7C68013 LIST OF FIGURES Figure Block Diagram 6 Figure Internal Code Memory, EA = 0 12 Figure External Code Memory, EA = 13 Figure Endpoint Configuration 15 Figure 19 Figure CY7C68013 128-pin TQFP Pin Assignment 20 Figure CY7C68013 100-pin TQFP Pin Assignment 21 Figure CY7C68013 56-pin SSOP Pin Assignment 22 Figure CY7C68013 56-pin QFN Pin Assignment 23 Figure Program Memory Read Timing 38 Figure Data Memory Read Timing Diagram 39 Figure Data Memory Write Timing Diagram 40 Figure GPIF Synchronous Signals Timing Diagram 41 Figure Slave FIFO Synchronous Read Timing Diagram 42 Figure Slave FIFO Asynchronous Read Timing Diagram 43 Figure Slave FIFO Synchronous Write Timing Diagram 43 Figure Slave FIFO Asynchronous Write Timing 44 Figure Slave FIFO Synchronous Packet End Strobe Timing Diagram 44 Figure Slave FIFO Asynchronous Packet End Strobe Timing Diagram 45 Figure Slave FIFO Output Enable Timing Diagram 45 Figure Slave FIFO Address to Flags/Data Timing Diagram 45 Figure Slave FIFO Synchronous Address Timing 46 Figure Slave FIFO Asynchronous Address Timing Diagram 46 Figure 56-lead Shrunk Small Outline Package O56 47 Figure 56-lead Quad Flatpack No Lead Package 8 x 8 mm 47 Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 48 Figure 128-Lead Thin Plastic Quad Flatpack 14 x 20 x mm A128 49 Figure Cross-section of the Area Underneath the QFN Package 50 Figure Plot of the Solder Mask White Area 50 Figure X-ray image of the assembly 51 Page 4 of 52 CY7C68013 LIST OF TABLES Table Special Function Registers 9 Table Default ID Values for FX2 9 Table INT2 USB Interrupts 10 Table Individual FIFO/GPIF Interrupt Sources 11 Table Default Full-Speed Alternate Settings 15 Table Default High-Speed Alternate Settings 16 Table Strap Boot EEPROM Address Lines to These Values 18 Table FX2 Pin Descriptions 24 Table FX2 Register Summary 31 Table DC Characteristics 37 Table Program Memory Read Parameters 38 Table Data Memory Read Parameters 39 Table Data Memory Write Parameters 40 Table GPIF Synchronous Signals Parameters with Internally Sourced IFCLK 41 Table GPIF Synchronous Signals Parameters with Externally Sourced IFCLK 41 Table Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK 42 Table Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK 42 Table Slave FIFO Asynchronous Read Parameters 43 Table Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK 43 Table Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK 44 Table Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK 44 Table Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK 44 Table Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK 45 Table Slave FIFO Asynchronous Packet End Strobe Parameters 45 Table Slave FIFO Output Enable Parameters 45 Table Slave FIFO Address to Flags/Data Parameters 46 Table Slave FIFO Synchronous Address Parameters 46 Table Slave FIFO Asynchronous Address Parameters 46 Table Ordering Information 46 Page 5 of 52 CY7C68013 EZ-USB Features Cypress’s EZ-USB is the world’s first USB integrated microcontroller. By integrating the USB transceiver, SIE, enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very costeffective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer rates of 56 Mbytes per second, the maximum allowable USB bandwidth, while still using a low-cost 8051 microcontroller in a package as small as a 56 SSOP. Because it incorporates the USB transceiver, the FX2 is more economical, providing a smaller footprint solution than USB SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE handles most of the USB and protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface GPIF and Master/Slave Endpoint FIFO 8- or 16-bit data bus provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. Four packages are defined for the family 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP. 24 MHz Ext. XTAL High-performance micro using standard tools with lower-power options Data 8 Address 16 x20 PLL 1.5k connected for full speed Integrated full- and high-speed XCVR USB XCVR CY Smart USB Engine 8051 Core 12/24/48 MHz, four clocks/cycle kB RAM Address 16 / Data Bus 8 I2C Compatible Master Additional I/Os 24 ADDR 9 GPIF RDY 6 CTL 6 Abundant I/O including two USARTS General programmable I/F to ASIC/DSP or bus standards such as ATAPI, EPP, etc. 8/16 FIFO Up to 96 MBytes/s burst rate Enhanced USB core Simplifies 8051 core “Soft Configuration” Easy firmware changes FIFO and endpoint memory master or slave operation Figure Block Diagram • Single-chip integrated USB Transceiver, SIE, and Enhanced 8051 Microprocessor • Software 8051 runs from internal RAM, which is: Downloaded via USB, or Loaded from EEPROM External memory device 128-pin configuration only • Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints Buffering options double, triple and quad • 8- or 16-bit external data interface • GPIF Allows direct connection to most parallel interfaces 8- and 16-bit Programmable waveform descriptors and configuration registers to define waveforms Supports multiple Ready RDY inputs and Control CTL outputs • Integrated, industry standard 8051 with enhanced features Up to 48-MHz clock rate Four clocks per instruction cycle Two USARTS Page 6 of 52 CY7C68013 Three counter/timers Expanded interrupt system Two data pointers • Supports bus powered applications by using renumeration • 3.3V operation • Smart Serial Interface Engine • Vectored USB interrupts • Separate data buffers for the SETUP and DATA portions of a CONTROL transfer • Integrated I2C-compatible controller, runs at 100 or 400 kHz • 48-MHz, 24-MHz, or 12-MHz 8051 operation • Four integrated FIFOs Brings glue and FIFOs inside for lower system cost Automatic conversion to and from 16-bit buses Master or slave operation FIFOs can use externally supplied clock or asynchronous strobes Easy interface to ASIC and DSP ICs • Special autovectors for FIFO and GPIF interrupts • Up to 40 general purpose I/Os • Four package TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP. • DSL modems • ATA interface • Memory card readers • Legacy conversion devices • Cameras • Scanners • Home PNA • Wireless LAN • MP3 players • Networking. The “Reference Designs” section of the cypress website provides additional tools for typical USB applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit for more information. Ordering Information Table Ordering Information Ordering Code CY7C68013-128AC CY7C68013-100AC CY7C68013-56PVC CY7C68013-56LFC CY3681 Package Type 128 TQFP 100 TQFP 56 SSOP 56 QFN EZ-USB FX2 Xcelerator Development Kit RAM Size 8K # Prog I/Os 40 24 8051 Address /Data Busses 16/8 bit Page 46 of 52 Package Diagrams The FX2 is available in four packages • 56-pin SSOP • 56-pin QFN • 100-pin TQFP • 128-pin TQFP. CY7C68013 Figure 56-lead Shrunk Small Outline Package O56 51-85062-C 51-85144-B Page 47 of 52 CY7C68013 Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 51-85050-A Page 48 of 52 CY7C68013 51-85101-B Figure 128-Lead Thin Plastic Quad Flatpack 14 x 20 x mm A128 Page 49 of 52 CY7C68013 PCB Layout Recommendations[17] The following recommendations should be followed to ensure reliable high-performance operation. • At least a four-layer impedance controlled boards are required to maintain signal quality. • Specify impedance targets ask your board vendor what they can achieve . • To control impedance, maintain trace widths and trace spacing. • Minimize stubs to minimize reflected signals. • Connections between the USB connector shell and signal ground must be done near the USB connector. • Bypass/flyback caps on VBus, near connector, are recommended. • DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20-30 mm. • Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. • It is preferred is to have no vias placed on the DPLUS or DMINUS trace routing. • Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. Quad Flat Package No Leads QFN Package Design Notes Electrical contact of the part to the Printed Circuit Board PCB is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper Cu fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the FX2 through the device’s metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process. For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s MicroLeadFrame MLF Technology.” This application note can be downloaded from AMKOR’s website from the following URL The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc. Figure 13-1 below display a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that “No Clean”, type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow. Cu Fill Solder Mask Cu Fill PCB Material PCB Material Via hole for thermally connecting the QFN to the circuit board ground plane. This figure only shows the top three layers of the circuit board Top Solder, PCB Dielectric, and the Ground Plane Figure Cross-section of the Area Underneath the QFN Package Figure 13-2 is a plot of the solder mask pattern and Figure 13-3 displays an X-Ray image of the assembly darker areas indicate solder. Figure Plot of the Solder Mask White Area Note Source for recommendations EZ-USB FX2 PCB Design Recommendations, and High

PDF Datasheet Preview

CY7C68013

CY7C68013 EZ-USB FX2 USB Microcontroller High-speed USB Peripheral Controller
3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C68013

TABLE OF CONTENTS

EZ-USB FX2 FEATURES 6

APPLICATIONS 7

FUNCTIONAL OVERVIEW 7

USB Signaling Speed 7 8051 Microprocessor 7 I2C-compatible Bus 8 Buses 8 USB Boot Methods 9 ReNumeration 9 Bus Powered Applications 9 Interrupt System 10 Reset and Wakeup 11 Program/Data RAM 11 Register Addresses 14 Endpoint RAM 14 External FIFO interface 16 GPIF 16 USB Uploads and Downloads 17 Autopointer Access 17 I2C-compatible Controller 17

PIN ASSIGNMENTS 18

CY7C68013 Pin Descriptions 24

REGISTER SUMMARY 31

ABSOLUTE MAXIMUM RATINGS 37

OPERATING CONDITIONS 37

DC CHARACTERISTICS 37

USB Transceiver 37

AC ELECTRICAL CHARACTERISTICS 38

USB Transceiver 38 Program Memory Read 38 Data Memory Read 39 Data Memory Write 40 GPIF Synchronous Signals 41 Slave FIFO Synchronous Read 42 Slave FIFO Asynchronous Read 43 Slave FIFO Synchronous Write 43 Slave FIFO Asynchronous Write 44 Slave FIFO Synchronous Packet End Strobe 44 Slave FIFO Asynchronous Packet End Strobe 45 Slave FIFO Output Enable 45 Slave FIFO Address to Flags/Data 45 Slave FIFO Synchronous Address 46 Slave FIFO Asynchronous Address 46

Page 2 of 52

CY7C68013
ORDERING INFORMATION 46 PACKAGE DIAGRAMS 47 PCB LAYOUT RECOMMENDATIONS 50 QUAD FLAT PACKAGE NO LEADS QFN PACKAGE DESIGN NOTES 50

Page 3 of 52

CY7C68013

LIST OF FIGURES

Figure Block Diagram 6 Figure Internal Code Memory, EA = 0 12 Figure External Code Memory, EA = 13 Figure Endpoint Configuration 15 Figure 19 Figure CY7C68013 128-pin TQFP Pin Assignment 20 Figure CY7C68013 100-pin TQFP Pin Assignment 21 Figure CY7C68013 56-pin SSOP Pin Assignment 22 Figure CY7C68013 56-pin QFN Pin Assignment 23 Figure Program Memory Read Timing 38 Figure Data Memory Read Timing Diagram 39 Figure Data Memory Write Timing Diagram 40 Figure GPIF Synchronous Signals Timing Diagram 41 Figure Slave FIFO Synchronous Read Timing Diagram 42 Figure Slave FIFO Asynchronous Read Timing Diagram 43 Figure Slave FIFO Synchronous Write Timing Diagram 43 Figure Slave FIFO Asynchronous Write Timing 44 Figure Slave FIFO Synchronous Packet End Strobe Timing Diagram 44 Figure Slave FIFO Asynchronous Packet End Strobe Timing Diagram 45 Figure Slave FIFO Output Enable Timing Diagram 45 Figure Slave FIFO Address to Flags/Data Timing Diagram 45 Figure Slave FIFO Synchronous Address Timing 46 Figure Slave FIFO Asynchronous Address Timing Diagram 46 Figure 56-lead Shrunk Small Outline Package O56 47 Figure 56-lead Quad Flatpack No Lead Package 8 x 8 mm 47 Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 48 Figure 128-Lead Thin Plastic Quad Flatpack 14 x 20 x mm A128 49 Figure Cross-section of the Area Underneath the QFN Package 50 Figure Plot of the Solder Mask White Area 50 Figure X-ray image of the assembly 51

Page 4 of 52

CY7C68013

LIST OF TABLES
Table Special Function Registers 9 Table Default ID Values for FX2 9 Table INT2 USB Interrupts 10 Table Individual FIFO/GPIF Interrupt Sources 11 Table Default Full-Speed Alternate Settings 15 Table Default High-Speed Alternate Settings 16 Table Strap Boot EEPROM Address Lines to These Values 18 Table FX2 Pin Descriptions 24 Table FX2 Register Summary 31 Table DC Characteristics 37 Table Program Memory Read Parameters 38 Table Data Memory Read Parameters 39 Table Data Memory Write Parameters 40 Table GPIF Synchronous Signals Parameters with Internally Sourced IFCLK 41 Table GPIF Synchronous Signals Parameters with Externally Sourced IFCLK 41 Table Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK 42 Table Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK 42 Table Slave FIFO Asynchronous Read Parameters 43 Table Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK 43 Table Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK 44 Table Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK 44 Table Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK 44 Table Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK 45 Table Slave FIFO Asynchronous Packet End Strobe Parameters 45 Table Slave FIFO Output Enable Parameters 45 Table Slave FIFO Address to Flags/Data Parameters 46 Table Slave FIFO Synchronous Address Parameters 46 Table Slave FIFO Asynchronous Address Parameters 46 Table Ordering Information 46

Page 5 of 52

CY7C68013

EZ-USB Features

Cypress’s EZ-USB is the world’s first USB integrated microcontroller. By integrating the USB transceiver, SIE, enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very costeffective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer rates of 56 Mbytes per second, the maximum allowable USB bandwidth, while still using a low-cost 8051 microcontroller in a package as small as a 56 SSOP. Because it incorporates the USB transceiver, the FX2 is more economical, providing a smaller footprint solution than USB SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE handles most of the USB and protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface GPIF and Master/Slave Endpoint FIFO 8- or 16-bit data bus provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.

Four packages are defined for the family 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.
24 MHz Ext. XTAL

High-performance micro using standard tools with lower-power options

Data 8

Address 16
x20 PLL
1.5k
connected for full speed

Integrated full- and high-speed

XCVR

USB XCVR

CY Smart USB Engine
8051 Core 12/24/48 MHz, four clocks/cycle
kB RAM

Address 16 / Data Bus 8

I2C Compatible

Master

Additional I/Os 24

ADDR 9

GPIF

RDY 6 CTL 6

Abundant I/O including two USARTS

General programmable I/F to ASIC/DSP or bus standards such as ATAPI, EPP, etc.
8/16

FIFO

Up to 96 MBytes/s burst rate

Enhanced USB core Simplifies 8051 core
“Soft Configuration” Easy firmware changes

FIFO and endpoint memory master or slave operation

Figure Block Diagram
• Single-chip integrated USB Transceiver, SIE, and Enhanced 8051 Microprocessor
• Software 8051 runs from internal RAM, which is:

Downloaded via USB, or Loaded from EEPROM External memory device 128-pin configuration only
• Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints Buffering options double, triple and quad
• 8- or 16-bit external data interface
• GPIF Allows direct connection to most parallel interfaces 8- and 16-bit Programmable waveform descriptors and configuration registers to define waveforms Supports multiple Ready RDY inputs and Control CTL outputs
• Integrated, industry standard 8051 with enhanced features Up to 48-MHz clock rate Four clocks per instruction cycle Two USARTS

Page 6 of 52

CY7C68013

Three counter/timers Expanded interrupt system Two data pointers
• Supports bus powered applications by using renumeration
• 3.3V operation
• Smart Serial Interface Engine
• Vectored USB interrupts
• Separate data buffers for the SETUP and DATA portions of a CONTROL transfer
• Integrated I2C-compatible controller, runs at 100 or 400 kHz
• 48-MHz, 24-MHz, or 12-MHz 8051 operation
• Four integrated FIFOs Brings glue and FIFOs inside for lower system cost Automatic conversion to and from 16-bit buses Master or slave operation FIFOs can use externally supplied clock or asynchronous strobes Easy interface to ASIC and DSP ICs
• Special autovectors for FIFO and GPIF interrupts
• Up to 40 general purpose I/Os
• Four package TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP.
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking. The “Reference Designs” section of the cypress website provides additional tools for typical USB applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit for more information.
Ordering Information
Table Ordering Information
Ordering Code CY7C68013-128AC CY7C68013-100AC CY7C68013-56PVC CY7C68013-56LFC CY3681

Package Type 128 TQFP 100 TQFP 56 SSOP 56 QFN EZ-USB FX2 Xcelerator Development Kit

RAM Size 8K
# Prog I/Os 40 24
8051 Address /Data Busses
16/8 bit

Page 46 of 52

Package Diagrams

The FX2 is available in four packages
• 56-pin SSOP
• 56-pin QFN
• 100-pin TQFP
• 128-pin TQFP.

CY7C68013

Figure 56-lead Shrunk Small Outline Package O56
51-85062-*C
51-85144-*B

Page 47 of 52

CY7C68013

Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101
51-85050-*A

Page 48 of 52

CY7C68013
51-85101-*B

Figure 128-Lead Thin Plastic Quad Flatpack 14 x 20 x mm A128

Page 49 of 52

CY7C68013

PCB Layout Recommendations[17]

The following recommendations should be followed to ensure reliable high-performance operation.
• At least a four-layer impedance controlled boards are required to maintain signal quality.
• Specify impedance targets ask your board vendor what they can achieve .
• To control impedance, maintain trace widths and trace spacing.
• Minimize stubs to minimize reflected signals.
• Connections between the USB connector shell and signal ground must be done near the USB connector.
• Bypass/flyback caps on VBus, near connector, are recommended.
• DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20-30 mm.
• Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces.
• It is preferred is to have no vias placed on the DPLUS or DMINUS trace routing.
• Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

Quad Flat Package No Leads QFN Package Design Notes

Electrical contact of the part to the Printed Circuit Board PCB is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper Cu fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the FX2 through the device’s metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated through hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process.

For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s MicroLeadFrame MLF Technology.” This application note can be downloaded from AMKOR’s website from the following URL The application note provides detailed information on board mounting guidelines, soldering flow, rework process, etc.

Figure 13-1 below display a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that “No Clean”, type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow.

Cu Fill

Solder Mask

Cu Fill

PCB Material

PCB Material

Via hole for thermally connecting the QFN to the circuit board ground plane.

This figure only shows the top three layers of the circuit board Top Solder, PCB Dielectric, and the Ground Plane

Figure Cross-section of the Area Underneath the QFN Package

Figure 13-2 is a plot of the solder mask pattern and Figure 13-3 displays an X-Ray image of the assembly darker areas indicate solder.

Figure Plot of the Solder Mask White Area

Note Source for recommendations EZ-USB FX2 PCB Design Recommendations, and High

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C68013-56PVC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C68013-56PVC 508140