RD1-4020 DisplayPort to DVI output
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RD1-4020 (pdf) |
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RD1-4020 DisplayPort to DVI output User Guide MegaChips’ Proprietary and Confidential This information shall not be shared or distributed outside the company and will be exchanged based on the signed proprietary information exchange agreement. MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips does not assume any responsibility or liability arising out of application or use of any product or service described herein except as explicitly agreed upon. MegaChips’ Proprietary Information Strictly Confidential Page 1 of 16 Contents RD1-4020 Purpose and scope 4 Set up instructions 4 I2C host 5 In-System Programming ISP 5 6 Board description 7 Principal components and functions 9 Connector descriptions 10 Switches 14 Stuffing options 14 B0546-GUD-01 MegaChips’ Proprietary Information Strictly Confidential Page 2 of 16 RD1-4020 List of tables List of figures Figure Connection set up 5 Block diagram Error! Bookmark not defined. Board Error! Bookmark not defined. B0546-GUD-01 MegaChips’ Proprietary Information Strictly Confidential Page 3 of 16 RD1-4020 Purpose and scope This document provides description and setup instructions for the Receiver STDP4020 reference design board [RD1-4020_400-530] targeted for DP to DVI conversion applications. The STDP4020 is an integrated circuit featuring a four lane DisplayPort receiver, quad LVDS & LVTTL transmitter with I2S and SPDIF audio outputs for digital audio-video conversion application. This device also includes SPI interface, I2C Slave Host Interface , I2C Master Interface, UART GProbe interface, and general-purpose IO pins. The RD1-4020 is a low cost compact four layer board that includes necessary interfaces and features to fully demonstrate the STDP4020 receiver functionalities. The RD1-4020 board includes discrete TMDS transmitter chips, converting LVTTL output from STDP4020 into DVI. This board is capable of handling both single link and dual link DVI output supporting video resolution from 640 x 480 up to 2560 x The RD1-4020 also features digital audio outputs SPIDIF and I2S up to 8 Ch. This reference design meets the following objectives: Stand-alone operation Includes the necessary firmware either IROM or external SPI to work independently this means the intended functionalities are performed without depending on external Host controllers. Slave configuration Provision to configure the device by an external Host controller through the Host Interface to I2C most likely when no SPI Flash is used . Set up instructions The picture below [Figure 1] is a connection diagram showing the RD1-4020 board used for transferring a PC DisplayPort signal into a dual link DVI output. Software utility GProbe tool ver 5.7.X.X , WinI2C tool B0546-GUD-01 MegaChips’ Proprietary Information Strictly Confidential Page 4 of 16 Figure Connection diagram PC DP signal to dual link DVI output RD1-4020 This board uses the standard DisplayPort connector recommended in the DP specification to connect the DisplayPort output from the PC to the input of the RD1-4020 board, and a dual link DVI connector to interface with a commercial DVI monitor. Connect the DisplayPort output from a PC source to the RD1-4020 reference board using a DP cable. Connect the output to a DVI monitor using a DVI cable. Connect the 12 V 4A DC power brick supplied for powering the board. A DisplayPort source that supports DP-Audio transmission is recommended for testing digital audio output of the RD1-4020 board. Once the connection is established, power ON the PC, DVI display, and the RD1-4020 DP receiver board. An image should pop up on the screen within 5-6 seconds. I2C host port Host connector CN401 allows configuration of the STDP4020 IC from an external host microcontroller through conventional I2C interface. User can plug two wires into pin 5 and pin 6 of this connector to access the I2C port of the chip. STDP4020 default device ID is 0xE6/0xE7, but can be changed through bootstrap settings. Refer to the STDP4020 datasheet for further details. In-System Programming ISP |
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