DS2430AX-S/T&R

DS2430AX-S/T&R Datasheet

DS2430A 256-Bit 1-Wire EEPROM

Part	Datasheet
DS2430AX-S/T&R	DS2430AX-S/T&R (pdf)

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DS2430A 256-Bit 1-Wire EEPROM § 256-bit Electrically Erasable Programmable Read Only Memory EEPROM plus 64-bit one-time programmable application register § Unique, factory-lasered and tested 64-bit registration number 8-bit family code + 48-bit serial number + 8-bit CRC tester assures absolute identity because no two parts are alike § Built-in multidrop controller ensures compatibility with other MicroLAN products § EEPROM organized as one page of 32 bytes for random access § Reduces control, address, data, and power to a single data pin § Directly connects to a single port pin of a microprocessor and communicates at up to 16.3kbits per second § 8-bit family code specifies DS2430A communication requirements to reader § Presence detector acknowledges when reader first applies voltage § Low cost TO-92 or 6-pin TSOC surface mount package § Reads and writes over a wide voltage range of 2.8V to 6.0V from -40°C to +85°C ORDERING INFORMATION DS2430A TO-92 package DS2430AP 6-pin TSOC package DS2430A/T&R Tape & Reel version of DS2430A DS2430AP/T&R Tape & Reel version of DS2430AP DS2430AX Chip Scale Pkg., 10k Tape & Reel DS2430AX-S Chip Scale Pkg., 2.5k Tape & Reel PIN ASSIGNMENT TO-92 DALLAS DS2430A TSOC PACKAGE TOP VIEW 3.7mm x 4.0mm x 1.5mm SIDE VIEW See Mech. Drawing Section BOTTOM VIEW See Mech. Drawings Section PIN DESCRIPTION TO-92 TSOC Pin 1 Ground Pin 2 Data Data Pin 3 NC Pin 4 Pin 5 Pin 6 1 of 16 111005 DS2430A SILICON LABEL DESCRIPTION OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2430A. The DS2430A has four main data components 1 64-bit lasered ROM, 2 256-bit EEPROM data memory with scratchpad, 3 64-bit one-time programmable application register with scratchpad and 4 8-bit status memory. The hierarchical structure of the 1-Wire protocol is shown in Figure The bus master must first provide one of the four ROM Function Commands 1 Read ROM, 2 Match ROM, 3 Search ROM, 4 Skip ROM. The protocol required for these ROM Function Commands is described in Figure After a ROM Function Command is successfully executed, the memory functions become accessible and the master can provide any one of the four memory function commands. The protocol for these memory function commands is described in Figure All data is read and written least significant bit first. 64-BIT LASERED ROM

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DS2430A 256-Bit 1-Wire EEPROM
§ 256-bit Electrically Erasable Programmable Read Only Memory EEPROM plus 64-bit one-time programmable application register
§ Unique, factory-lasered and tested 64-bit registration number 8-bit family code + 48-bit serial number + 8-bit CRC tester assures absolute identity because no two parts are alike
§ Built-in multidrop controller ensures compatibility with other MicroLAN products
§ EEPROM organized as one page of 32 bytes for random access
§ Reduces control, address, data, and power to a single data pin
§ Directly connects to a single port pin of a microprocessor and communicates at up to 16.3kbits per second
§ 8-bit family code specifies DS2430A communication requirements to reader
§ Presence detector acknowledges when reader first applies voltage
§ Low cost TO-92 or 6-pin TSOC surface mount package
§ Reads and writes over a wide voltage range of 2.8V to 6.0V from -40°C to +85°C
ORDERING INFORMATION

DS2430A

TO-92 package

DS2430AP
6-pin TSOC package

DS2430A/T&R

Tape & Reel version of

DS2430A

DS2430AP/T&R Tape & Reel version of

DS2430AP

DS2430AX

Chip Scale Pkg., 10k Tape
& Reel

DS2430AX-S

Chip Scale Pkg., 2.5k Tape
& Reel

PIN ASSIGNMENT

TO-92

DALLAS DS2430A

TSOC PACKAGE

TOP VIEW 3.7mm x 4.0mm x 1.5mm

SIDE VIEW

See Mech. Drawing Section

BOTTOM VIEW See Mech.

Drawings Section

PIN DESCRIPTION

TO-92 TSOC

Pin 1 Ground

Pin 2 Data

Data

Pin 3 NC

Pin 4

Pin 5

Pin 6
1 of 16
111005

DS2430A

SILICON LABEL DESCRIPTION

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2430A. The DS2430A has four main data components 1 64-bit lasered ROM, 2 256-bit EEPROM data memory with scratchpad, 3 64-bit one-time programmable application register with scratchpad and 4 8-bit status memory. The hierarchical structure of the 1-Wire protocol is shown in Figure The bus master must first provide one of the four ROM Function Commands 1 Read ROM, 2 Match ROM, 3 Search ROM, 4 Skip ROM. The protocol required for these ROM Function Commands is described in Figure After a ROM Function Command is successfully executed, the memory functions become accessible and the master can provide any one of the four memory function commands. The protocol for these memory function commands is described in Figure All data is read and written least significant bit first.
64-BIT LASERED ROM

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Datasheet ID: DS2430AX-S/T&R 647170