IXTH 7P50 IXTH 8P50
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IXTH7P50 (pdf) |
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Standard Power MOSFET P-Channel Enhancement Mode Avalanche Rated IXTH 7P50 IXTH 8P50 V IR DSS D25 DS on -500V -7 A -500V -8 A Symbol V V DGR VGS VGSM ID25 EAR PD T T stg Md Weight Test Conditions TJ = 25°C to 150°C TJ = 25°C to 150°C RGS = 1 Continuous Transient TC = 25°C TC = 25°C, pulse width limited by TJ TC = 25°C TC = 25°C TC = 25°C Maximum lead temperature for soldering mm in. from case for 10 s Mounting torque Maximum Ratings -500 -500 ±20 ±30 7P50 8P50 7P50 8P50 7P50 8P50 -55 +150 -55 +150 Nm/lb.in. TO-247 AD D TAB G = Gate, S = Source, D = Drain, TAB = Drain • International standard package JEDEC TO-247 AD • Low RDS on HDMOSTM process •Rugged polysilicon gate cell structure •Unclamped Inductive Switching UIS rated •Low package inductance <5 nH - easy to drive and to protect V DSS V GS th IGSS I |
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