- IS39LV040 512K x 8 4 Mbit - IS39LV010 128K x 8 1 Mbit - IS39LV512 64K x 8 512 Kbit
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IS39LV512-70VCE (pdf) |
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IS39LV010-70VCE |
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IS39LV010-70JCE |
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IS39LV512-70JCE |
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IS39LV040-70JCE |
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IS39LV040-70VCE |
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Power Supply Operation - Low voltage range V - V - IS39LV040 512K x 8 4 Mbit - IS39LV010 128K x 8 1 Mbit - IS39LV512 64K x 8 512 Kbit - 70 ns access time - Uniform 4 Kbyte sectors - Uniform 64 Kbyte blocks sector group - except IS39LV512 - Typical 16 us/byte programming time - Typical 55 ms sector/block/chip erase time - Typical 4 mA active read current - Typical 8 mA program/erase current - Typical uA CMOS standby current - 100,000 program/erase cycles per single sector - Minimum 20 years data retention - 32-pin 8 mm x 14 mm VSOP - 32-pin PLCC - Optional lead-free Pb-free package - IS39LV040/010/512 0oC~+85oC The IS39LV040/010/512 are 4 Mbit / 1 Mbit / 512 Kbit Volt-only Flash Memories. These devices are designed to use a single low voltage, range from Volt to Volt, power supply to perform read, erase and program operations. The Volt VPP power supply for program and erase operations are not required. The devices can be programmed in standard EPROM programmers as well. The memory array of IS39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory arrays of IS39LV010/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks sector group area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase operation. The devices have a standard microprocessor interface as well as a JEDEC standard pin-out/command set. The program operation is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by issuing the chip erase, block, or sector erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit functions, the progress or completion of program and erase operations can be detected by reading the Data# Polling on I/O7 or the Toggle Bit on I/O6. The IS39LV040/010/512 are manufactured on pFLASH ’s advanced nonvolatile CMOS technology. The devices are offered in 32-pin VSOP and PLCC packages with 70 ns access time. Integrated Silicon Solution, Inc. 07/29/2015 A18 VCC WE# A17 WE# WE# I S 3 9 L V 5 12 I S 3 9 L V 0 10 I S 3 9 L V 0 4 0 I S 3 9 L V 0 4 0 I S 3 9 L V 0 10 I S 3 9 L V 5 12 I/O0 I/O0 I/O0 4 3 2 1 32 31 30 14 15 16 17 18 19 20 I S 3 9 L V 5 12 I S 3 9 L V 0 10 I S 3 9 L V 0 4 0 OE# OE# CE# CE# I/O7 I/O7 I/O7 I/O6 I/O5 I/O4 I/O2 GND I/O3 I/O1 I/O6 I/O5 I/O4 PRODUCT ORDERING INFORMATION IS39LVxxx -70 J C E Environmental Attribute E = Lead-free Pb-free Package Blank = Standard Package Temperature Range C = 0°C to +85°C Package Type J = 32-pin PLCC V = 32-pin VSOP 8mm x 14mm Speed Option -70 = 70ns Device Number IS39LV040 4 Mbit IS39LV010 1 Mbit IS39LV512 512 Kbit Integrated Silicon Solution, Inc. 07/29/2015 0+] 100 IS39LV040-70JCE IS39LV040-70VCE IS39LV010-70JCE IS39LV010-70VCE IS39LV512-70JCE IS39LV512-70VCE 3DFNDJH 32-pin PLCC 32-pin VSOP 32-pin PLCC 32-pin VSOP 32-pin PLCC 32-pin VSOP Integrated Silicon Solution, Inc. 07/29/2015 |
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