MT8VDDT12832UY-6F1
MT8VDDT12832UY-6F1 Datasheet
MT8VDDT3232U 128MB MT8VDDT6432U 256MB MT8VDDT12832U 512MB
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MT8VDDT12832UY-6F1 |
MT8VDDT12832UY-6F1 (pdf) |
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MT8VDDT6432UY-5K1 |
MT8VDDT6432UY-5K1 |
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| 128MB, 256MB, 512MB x32, DR 100-Pin DDR UDIMM Features DDR SDRAM Unbuffered DIMM MT8VDDT3232U 128MB MT8VDDT6432U 256MB MT8VDDT12832U 512MB For DDR SDRAM component specifications, please refer to the Web site: • 100-pin, dual in-line memory module DIMM • Fast data transfer rate PC2100 and PC2700 • Utilizes 266 MT/s or 333 MT/s DDR SDRAM components • 128MB 16 Meg x 32 , 256MB 32 Meg x 32 , 512MB 64 Meg x 32 • VDD = +2.5V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Auto Refresh and Self Refresh Modes • 15.625µs 128MB , 7.8125µs 256MB, 512MB maximum average periodic refresh interval • Gold edge contacts • Dual rank Figure 1 100-Pin DIMM MO-161 Options Marking • Package 100-pin DIMM standard 100-pin DIMM lead-free 1 • Operating Temperature Range Commercial ambient Industrial ambient • Frequency/CAS Latency2 6ns/167 MHz 333MT/s CL = 7.5ns/133 MHz 266 MT/s CL = 2 7.5ns/133 MHz 266 MT/s CL = None I -6 -75Z1 Notes Contact Micron for product availability. CL = CAS READ latency. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004, 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128MB, 256MB, 512MB x32, DR 100-Pin DDR UDIMM Features Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing MT8VDDT3232U 4K 4 BA0, BA1 128Mb 16 Meg x 8 1K 2 S0#, S1# MT8VDDT6432U 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 2 S0#, S1# MT8VDDT12832U 8K 4 BA0, BA1 512Mb 64 Meg x 8 1K A11 2 S0#, S1# Table 2 Part Numbers and Timing Parameters Module Memory Clock/ Latency Module Density Configuration Bandwidth Data Bit Rate CL - tRCD - tRP The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 5, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram, on page Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB x32, DR 100-Pin DDR UDIMM Mode Register Definition If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 4: Mode Register Definition Diagram 128MB Module Address Bus BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA1and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . 256MB, 512MB Module Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . Burst Length M2 M1 M0 M3 = 0 0 Reserved 1 0 Reserved 1 0 1 Reserved 1 0 Reserved 1 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004, 2005 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB x32, DR 100-Pin DDR UDIMM Mode Register Definition Table 5 Table 6: Burst Definition Table Starting Column Burst Length Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved A1 A0 |
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