IS42VM16160D-8BL-TR

IS42VM16160D-8BL-TR Datasheet

IS42VM83200D / IS42VM16160D / IS42VM32800D

Part	Datasheet
IS42VM16160D-8BL-TR	IS42VM16160D-8BL-TR (pdf)

Related Parts	Information
IS42VM16160D-8BLI	IS42VM16160D-8BLI
IS42VM16160D-8BL	IS42VM16160D-8BL
IS42VM16160D-8TLI	IS42VM16160D-8TLI
IS42VM16160D-8BLI-TR	IS42VM16160D-8BLI-TR

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IS42VM83200D / IS42VM16160D / IS42VM32800D 32Mx8, 16Mx16, 8Mx32 256Mb Mobile Synchronous DRAM FEATURES • Fully synchronous all signals referenced to a positive clock edge • Internal bank for hiding row access and pre- charge • Programmable CAS latency 2, 3 • Programmable Burst Length 1, 2, 4, 8, and Full Page • Programmable Burst Sequence • Sequential and Interleave • Auto Refresh CBR • TCSR Temperature Compensated Self Refresh • PASR Partial Arrays Self Refresh 1/16, 1/8, 1/4, 1/2, and Full • Deep Power Down Mode DPD • Driver Strength Control DS 1/4, 1/2, and Full OPTIONS • Configurations: 32M x 8 16M x 16 8M x 32 • Power Supply IS42VMxxx Vdd/Vddq = 1.8V • Packages x8 II 54 x16 II 54 , BGA 54 x32 TSOP II 86 , BGA 90 • Temperature Range Commercial 0°C to +70°C Industrial ºC to 85 ºC APRIL 2012 ISSI's 256Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 256Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products. KEY TIMING PARAMETERS Parameter -8 1 -12 2 Unit CLK Cycle Time CAS Latency = 3 12 ns CAS Latency = 2 CLK Frequency CAS Latency = 3 125 83 Mhz CAS Latency = 2 - Mhz Access Time from CLK CAS Latency = 3 10 ns CAS Latency = 2 Notes Available for x8/x16 only Available for x32 only ADDRESSING TABLE Parameter Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing 32M x 8 8M x 8 x 4 banks 8K/64ms A0-A12 A0-A9 BA0, BA1 A10 16M x 16 4M x 16 x 4 banks 8K/64ms A0-A12 A0-A8 BA0, BA1 A10 8M x 32 2M x 32 x 4 banks 4K/64ms A0-A11 A0-A8 BA0, BA1 A10 Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that a. the risk of injury or damage has been minimized b. the user assume all such risks and c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. - 04/11/2012 The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. Burst Definition Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved A 1 A 0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 A2 A1 A0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full n = A0-A8 x16, x32 Page n = A0-A9 x8 y location 0-y Cn + 3, Cn + - 1, Cn, Cn + 1, Cn + 2 Not Supported CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Integrated Silicon Solution, Inc. - Ordering Information Vdd = 1.8V Commercial Range 0°C to +70°C Configuration 16Mx16 8Mx32 Frequency MHz 125 83 Speed ns 8 12 Order Part No. IS42VM16160D-8BL IS42VM32800D-12BL Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free Industrial Range to 85ºC Configuration Frequency MHz Speed ns 32Mx8 16Mx16 8Mx32 Order Part No. IS42VM83200D-8TLI IS42VM16160D-8TLI IS42VM16160D-8BLI IS42VM32800D-12TLI IS42VM32800D-12BLI Note Contact ISSI for leaded parts support. Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Integrated Silicon Solution, Inc. - 04/11/2012 IS42VM83200D / IS42VM16160D / IS42VM32800D Integrated Silicon Solution, Inc. - 04/11/2012 IS42VM83200D / IS42VM16160D / IS42VM32800D 08/29/2008 NOTE : CONTROLLING DIMENSION MM Reference document JEDEC MS-207 Integrated Silicon Solution, Inc. - 04/11/2012 IS42VM83200D / IS42VM16160D / IS42VM32800D Integrated Silicon Solution, Inc. - NOTE : Controlling dimension mm Dimension D and E1 do not include mold protrusion Dimension b does not include dambar protrusion/intrusion. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 04/11/2012 09/26/2006 IS42VM83200D / IS42VM16160D / IS42VM32800D 08/14/2008 NOTE : CONTROLLING DIMENSION MM Reference document JEDEC MO-207 Integrated Silicon Solution, Inc. - 04/11/2012

PDF Datasheet Preview

IS42VM83200D / IS42VM16160D / IS42VM32800D
32Mx8, 16Mx16, 8Mx32 256Mb Mobile Synchronous DRAM

FEATURES
• Fully synchronous all signals referenced to a
positive clock edge
• Internal bank for hiding row access and pre-
charge
• Programmable CAS latency 2, 3
• Programmable Burst Length 1, 2, 4, 8, and Full

Page
• Programmable Burst Sequence
• Sequential and Interleave
• Auto Refresh CBR
• TCSR Temperature Compensated Self Refresh
• PASR Partial Arrays Self Refresh 1/16, 1/8,
1/4, 1/2, and Full
• Deep Power Down Mode DPD
• Driver Strength Control DS 1/4, 1/2, and Full

OPTIONS
• Configurations:
32M x 8 16M x 16 8M x 32
• Power Supply IS42VMxxx Vdd/Vddq = 1.8V
• Packages x8 II 54 x16 II 54 , BGA 54 x32 TSOP II 86 , BGA 90
• Temperature Range Commercial 0°C to +70°C Industrial ºC to 85 ºC

APRIL 2012

ISSI's 256Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 256Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products.

KEY TIMING PARAMETERS

Parameter
-8 1 -12 2 Unit

CLK Cycle Time

CAS Latency = 3
12 ns

CAS Latency = 2

CLK Frequency

CAS Latency = 3
125 83 Mhz

CAS Latency = 2
- Mhz

Access Time from CLK

CAS Latency = 3
10 ns

CAS Latency = 2

Notes Available for x8/x16 only Available for x32 only

ADDRESSING TABLE

Parameter

Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing
32M x 8
8M x 8 x 4 banks 8K/64ms A0-A12 A0-A9 BA0, BA1 A10
16M x 16
4M x 16 x 4 banks 8K/64ms A0-A12 A0-A8 BA0, BA1 A10
8M x 32
2M x 32 x 4 banks 4K/64ms A0-A11 A0-A8 BA0, BA1 A10

Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that a. the risk of injury or damage has been minimized b. the user assume all such risks and c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. -
04/11/2012
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table.

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address

Type = Sequential Type = Interleaved

A 1 A 0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0

A2 A1 A0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0

Full n = A0-A8 x16, x32 Page n = A0-A9 x8
y location 0-y

Cn + 3, Cn + - 1,

Cn, Cn + 1, Cn + 2

Not Supported

CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Integrated Silicon Solution, Inc. -
Ordering Information Vdd = 1.8V

Commercial Range 0°C to +70°C

Configuration 16Mx16 8Mx32

Frequency MHz 125 83

Speed ns 8 12

Order Part No. IS42VM16160D-8BL IS42VM32800D-12BL

Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free

Industrial Range to 85ºC

Configuration Frequency MHz Speed ns
32Mx8 16Mx16
8Mx32

Order Part No. IS42VM83200D-8TLI IS42VM16160D-8TLI IS42VM16160D-8BLI IS42VM32800D-12TLI IS42VM32800D-12BLI

Note Contact ISSI for leaded parts support.

Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free

Integrated Silicon Solution, Inc. -
04/11/2012

IS42VM83200D / IS42VM16160D / IS42VM32800D

Integrated Silicon Solution, Inc. -
04/11/2012

IS42VM83200D / IS42VM16160D / IS42VM32800D
08/29/2008

NOTE :

CONTROLLING DIMENSION MM Reference document JEDEC MS-207

Integrated Silicon Solution, Inc. -
04/11/2012

IS42VM83200D / IS42VM16160D / IS42VM32800D

Integrated Silicon Solution, Inc. -

NOTE :

Controlling dimension mm

Dimension D and E1 do not include mold protrusion

Dimension b does not include dambar protrusion/intrusion.

Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
04/11/2012
09/26/2006

IS42VM83200D / IS42VM16160D / IS42VM32800D
08/14/2008

NOTE :

CONTROLLING DIMENSION MM Reference document JEDEC MO-207

Integrated Silicon Solution, Inc. -
04/11/2012

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS42VM16160D-8BL-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: IS42VM16160D-8BL-TR 639284