P95020ZNQG8

P95020ZNQG8 Datasheet

P95020

Part	Datasheet
P95020ZNQG8	P95020ZNQG8 (pdf)

Related Parts	Information
P95020ZLLG	P95020ZLLG
P95020ZLLG8	P95020ZLLG8
P95020ZNQG	P95020ZNQG

PDF Datasheet Preview
Audio, Power Management and Control P95020 Preliminary Datasheet OVERVIEW The P95020 is designed to provide maximum flexibility to system designers by providing full customization and programmability. It is the first of a new generation of standardized application-specific controllers that incorporates a general purpose microcontroller, a high fidelity audio CODEC including headphone outputs and a 2.5W Class D audio amplifier, full power management functionality, a touch screen controller and a real time clock all of which are required by portable consumer devices such as cellular phone handsets, portable gaming devices, digital media players, portable navigational devices, etc. The general purpose microcontroller controls the device power-on/power-off sequencing and can also be used for general system housekeeping. The P95020 includes two Interfaces, a master for communicating with an external EEPROM and a slave for communicating with the host. The high fidelity audio CODEC along with headphone outputs and the watt Class D audio speaker amplifier comprise a total audio solution for portable applications. The switch-mode EnergyPath Battery Charger operates with its own high efficiency buck regulator to transmit the watts available from a USB port to the system with minimal wasted power. It can also handle up to 2A from a wall charger. Its power management features along with switch-mode converters and LDOs should be sufficient to provide power for even the most complex hand-held devices. The integrated touch screen controller allows adding touch screen capability to devices at significantly reduced cost. It also includes IDT‟s high quality, low power real time clock. Smart Phones Portable Gaming Device Digital Media Players Portable Navigational Devices KEY FEATURES Quick Turn Customization Embedded Microcontroller Master Controller during Power Up & Power-Down • Initialization and power sequencing Dynamic Power Management via bus interface Up to 10 General Purpose I/Os available General house keeping for P95020 and other devices Audio Features 4 Channel CODEC with 24-bit resolution and internal registers for status and control Integrated Watt Mono Class D Amplifier with Filterless Operation. Stereo cap-less headphone driver Differential Analog Audio Line Inputs Dual Mode Microphone Inputs Analog or DMIC Battery Charging Circuit Autonomous Li-Ion/Li-Poly charger up to 1.5A • Automatic Load Prioritization • Advanced Battery Safety features High efficiency switch-mode *EnergyPath controller USB or Wall-mounted Charging • Programmable Current Limit • Automatic end-of-charge control Internal 180 ideal diode with external ideal diode controller Power Management Features All Converters • Power up/down sequence field reprogrammable with external EEPROM • Dynamic voltage scaling • Host or I2C output enable / disable Buck DC-DC PWM converters with PFM mode • Two at 500mA, 0.75V to 3.7V • One at 1000mA, 0.75V to 3.7V Boost DC-DC converters • One at A peak on inductor, 4.05V to 5.0V • One LED supply with 2 W total output power Two programmable current sinks, 25mA each Voltage limited to rating of external FET & diode Linear Regulators • Three LDOs at 150mA, 0.75V to 3.7V • Four LDOs at 50mA, 0.7V to 3.7V • One always-on LDO at 10mA, or 3.0V ADC and Touch Screen Controller 4-wire touch screen interface One direct battery measurement channel One direct VSYS measurement channel One direct charge current measurement channel On-Chip temperature measurement Four auxiliary analog input channels shared with GPIO pins Touch pressure measurement Sample rate 62.5k SPS 12 bit resolution, DNL -1~+2 LSB, INL +-2 On-chip 2.5V reference 2010 Integrated Device Technology, Inc. Pin MUX P95020 / Preliminary Datasheet BLOCK DIAGRAM Thermal Sensor Power-On-Reset SW_DET Real Time Clock 10 GPIOs ADC Touch Screen Controller LED_BOOST LED Backlight P/S with 2 Current Sinks Hot Swap Switches PLL & Clock Synthesizer I2C Slave I/F To External Processor Bus Arbitrator Micro Controller 1.5K Byte Program FUNCTIONAL MODES 19 REGISTER MAP 20 BYTE ORDERING AND OFFSET 21 REGISTER ACCESS TYPES 21 RESERVED BIT FIELDS 21 AUDIO MODULE 22 AUDIO - PIN 22 AUDIO - SECTION OVERVIEW 23 AUDIO - ANALOG PERFORMANCE CHARACTERISTICS 23 AUDIO - MICROPHONE INPUT PORT 24 AUDIO - ANALOG LINE 27 AUDIO - DAC, ADC 27 AUDIO - AUTOMATIC GAIN CONTROL 28 AUDIO - ANALOG MIXER BLOCK 28 AUDIO - DIGITAL AUDIO INPUT/OUTPUT INTERFACE 29 AUDIO - REFERENCE VOLTAGE GENERATOR, BUFFER, & FILTERING CAPS 31 AUDIO - ANALOG AND CLASS D OUTPUT BLOCK 31 AUDIO - CLASS-D BTL AMPLIFIER 32 AUDIO CLASS_D - REGISTERS 32 AUDIO CLASS_D - EQUALIZER COEFFICIENT & PRESCALER RAM EQRAM 39 AUDIO CONTROL REGISTERS 40 CHARGER MODULE 52 CHARGER - 52 CHARGER SUB-BLOCKS 52 CHARGER DC ELECTRICAL CHARACTERISTICS 53 CHARGER TYPICAL PERFORMANCE 54 CHARGER - REGISTER ADDRESSES 55 CHARGER - PRE-REGULATOR 58 IDEAL DIODE FROM VBAT TO VSYS 59 CHARGER - CHARGER/DISCHARGER 60 CHARGER - THERMAL MONITORING 60 CHARGER - POWER ON 60 CLOCK GENERATOR MODULE 61 CKGEN - PIN DEFINITIONS 61 CKGEN - OSCILLATOR CIRCUIT ELECTRICAL CHARACTERISTICS 62 CKGEN - PLL CONTROL 63 CKGEN OSCILLATOR CIRCUIT 63 CKGEN - CKGEN POWER SOURCE 63 CKGEN CLOCK 63 CKGEN CLOCK GENERATOR REGISTERS 64 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet RTC MODULE 66 RTC - GENERAL 66 RTC - TIMEKEEPER REGISTERS 67 RTC - DATE REGISTERS 67 RTC - ALARM REGISTERS 68 RTC - INTERRUPT REGISTERS 69 RTC RESERVED REGISTERS 70 GENERAL PURPOSE 71 GENERAL PURPOSE TIMERS GENERAL 71 GENERAL PURPOSE TIMERS 71 DC_DC MODULE 74 2MHz, 500mA & 1000mA SYNCHRONOUS BUCK REGULATORS 75 BUCK1000 & BUCK500 - PIN 76 BUCK1000 & BUCK500 - ELECTRICAL CHARACTERISTICS 76 BUCK CONVERTERS TYPICAL PERFORMANCE 77 BUCK1000 & BUCK500 - REGISTER 79 BUCK1000 & BUCK500 - ENABLING & DISABLING 80 BUCK1000 & BUCK500 - APPLICATIONS INFORMATION 81 HIGH EFFICIENCY 10 LED BOOST CONVERTER AND SINKS 83 LED_BOOST - ELECTRICAL CHARACTERISTICS 84 LED_BOOST TYPICAL PERFORMANCE CHARACTERISTICS 84 LED_BOOST - REGISTER SETTINGS 85 LED_BOOST - ENABLING & DISABLING 86 LED_BOOST Over-Voltage Protection 87 LED_BOOST Over-Current 87 LED_BOOST - APPLICATIONS 87 BOOST5 1.5A, SYNCHRONOUS PWM BOOST CONVERTER 89 BOOST5 - ELECTRICAL 90 BOOST5 - REGISTER 90 BOOST5 - ENABLING & DISABLING 91 OUTPUT 92 BOOST5 - APPLICATIONS INFORMATION 92 CLASS_D BTL POWER OUTPUT STAGE 93 CLASS_D - ELECTRICAL CHARACTERISTICS 93 CLASS_D TYPICAL PERFORMANCE CHARACTERISTICS 94 CLASS_D REGISTER SETTINGS 94 CLASS_D - AUDIO INTERFACE AND DECODE 95 CLASS_D - SHORT CIRCUIT PROTECTION CIRCUITRY 95 CLASS_D - APPLICATIONS 95 TSC MODULE - ADC AND TOUCH SCREEN CONTROLLER 96 ADC AND TOUCH SCREEN CONTROLLER ELECTRICAL CHARACTERISTICS 97 ADC AND TOUCH SCREEN CONTROLLER PIN DEFINITIONS 97 ADC AND TOUCH SCREEN CONTROLLER 97 ADC AND TOUCH SCREEN CONTROLLER REGISTERS 100 PCON MODULE POWER CONTROLLER AND GENERAL PURPOSE I/O 107 GPIO PIN DEFINITIONS 107 POWER STATES 107 POWER SEQUENCING BY EMBEDDED 107 POWER ON RESET OUTPUT POR_OUT 108 POWER SWITCH DETECTOR 108 GPIO GENERAL DESCRIPTION 108 PCON 108 HOTSWAP 113 HOT SWAP LOAD SWITCHES ELECTRICAL 113 HOTSWAP TYPICAL PERFORMANCE CHARACTERISTICS 114 HOTSWAP PIN 115 PCON REGISTER - HOTSWAP CONFIGURATION 115 I2C_I2S MODULE 116 I2C_I2S - PIN 116 INTERRUPT DISPATCHER 117 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet ACCESS ARBITER 117 DIGITAL AUDIO DATA SERIAL INTERFACE 117 I2C_I2S INTERFACE 118 GLOBAL REGISTER SETTINGS 0 120 ACCM REGISTERS 123 LDO MODULE 124 LDO - PIN DEFINITIONS 125 LDO - LDO_150 & LDO_050 ELECTRICAL CHARACTERISTICS 125 LDO TYPICAL PERFORMANCE CHARACTERISTICS 126 LDO - LDO_LP - ELECTRICAL 127 LDO - LIST OF ALL LDOS 127 LDO REGISTER SETTINGS 127 EMBUP EMBEDDED MICROCONTROLLER SUBSYSTEM & 131 FUNCTIONAL DESCRIPTION 131 ON-CHIP RAM & ROM 131 SLAVE INTERFACE 131 132 INTERRUPT 132 APPLICATIONS 133 EXTERNAL COMPONENTS 133 DIGITAL LOGIC DECOUPLING CAPACITORS 133 CLASS_D CONSIDERATIONS 133 SERIES TERMINATION RESISTORS 133 EXTERNAL RESISTOR CONNECTION 133 CRYSTAL LOAD CAPACITORS 133 PCB LAYOUT 133 POWER DISSIPATION AND THERMAL REQUIREMENTS 133 TYPICAL BLOCK PERFORMANCE CHARACTERISTICS GRAPHS 133 APPLICATIONS REFERENCE 134 SOLDERING 134 PACKAGE OUTLINE 134 LLG124 PACKAGE OUTLINE 134 NQG132 PACKAGE OUTLINE Exposed Die Paddle Size D2 = E2 = mm 135 ORDERING 135 TABLE OF FIGURES Figure 1 P95020 Block Diagram. 2 Figure 2 P95020 Pinout Diagram LLG124 7 Figure 3 P95020 Pinout 8 Figure 4 Overall System Functional Diagram. 18 Figure 5 Audio Block Diagram 22 Figure 6 Digital Microphone Mode 3 26 Figure 7 Digital Microphone Mode 1 & 27 Figure 8 Automatic Gain 28 Figure 9 Charger Block Diagram 52 Figure 10 Pre-Regulator Efficiency vs Load Current VBUS = 5.0V, VSYS = 54 Figure Pre-Regulator Load Regulation VBUS = 5.0V, VSYS = 3.7V 55 Figure 12 Battery Charge Current vs Temperature 55 Figure 13 VSYS Regulation Curve Tracking VBAT 59 Figure 14 Clock Generator Block Diagram 61 Figure 15 DC_DC Block Diagram 74 Figure 16 BUCK500 / BUCK1000 Block Diagram 76 Figure 17 BUCK500 DC-DC Regulator Efficiency vs Load Current PWM Mode 78 Figure 18 BUCK1000 DC-DC Regulator Efficiency vs Load Current PWM Mode 78 Figure 19 BUCK500 DC-DC Regulator Efficiency vs Load Current PFM 79 Figure 20 BUCK500 or BUCK 1000 Applications Diagram 81 Figure 21 White LED Boost & Sink Driver Block Diagram 83 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet Figure 22 LED Boost Efficiency vs Load Current two srings of 10 LEDs 84 Figure 23 LED Boost Efficiency vs VIN two srings of 10 LEDs 85 Figure 24 LED_BOOST Application 87 Figure 25 BOOST5 Block Diagram 89 Figure 26 BOOST5 Applications Diagram 92 Figure 27 Clss D BTL Efficiency vs Outpout Power 4 ohm speaker 94 Figure 28 ADC & Touchscreen Controller Block Diagram 96 Figure 29 Hotswap Block Diagram 113 Figure 30 Hotswap #1 ON Resistance vs Temperature 114 Figure 31 Hotswap #2 ON Resistance vs Temperature 114 Figure 32 I2C Read / Write Operation 117 Figure 33 LDO_050 / LDO_150 Block 124 Figure 34 LDO_050_n 50mA LDO Load Regulation 126 Figure 35 LDO_150_n 150mA LDO Load Regulation 126 Figure 36 - Top level Interrupt 132 Figure 37 Power Derating Curve 133 LIST OF TABLES Table 1 LLG124 Pin Functions by Pin Number See Figure 2 9 Table 2 - NQG132 Pin Functions by Pin Number see Figure 3 11 Table 3 Register Address Global Mapping 20 Table 4 - Valid Digital Mic Configurations 25 Table 5 - MCLK Rate selection MCLK_DIV2 MCLK_RATE 29 Table 6 MCLK/Sample Rate 30 Table 7 - EQRAM 39 Table 8 Register 0xA090 0x90 Current Limit I_LIM Settings Bits [2:0] 56 Table 9 Register 0xA091, 0x91 Charging Maximum Voltage CHG_VOL Settings, Bits 56 Table 10 Register 0xA091, 0x91 Charging Current Limit via Sense Resistor CHG_CUR Settings, Bits [3:0] 56 Table 11 Register 0xA092 0x92 Charging Termination Time CHG_TERM Settings Bits [1:0] 56 Table 12 Register 0xA093 0x93 Battery Recovery Charge Current Control Settings Bits 57 Table 13 Register 0xA093, 0x93 Battery Good Voltage Threshold Settings, Bits [4:3] 57 Table 14 Register 0xA095, 0x95 Current Charger Mode Settings, Bits [4:3] 57 Table 15 - Crystal 63 Table 16 - Alarm mask bits 66 Table 17 DC-DC Block Registers Including the CLASS_D BTL Power 74 Table 18 BUCK500_0, BUCK500_1 and BUCK1000 Register Addresses 79 Table 19 Output Voltage Register Settings, Bits [6:0] 79 Table 20 Control Register Cycle by Cycle Current Limit I_LIM Settings for Bits [3:2] [Note ] 80 Table 21 Interoperability of enabling/disabling methods vs. loading default values. 80 Table 22 Register 0xA086 0x86 IOUT Current Settings for Bits [4:0], Half Scale and Full Scale................................... 85 Table 23 Interoperability of enabling/disabling methods vs. loading default values. 86 Table 24 Register 0xA088 Output Voltage Bit Setting [4:0] 90 Table 25 Register 0xA089 0x89 Peak Current Limit I_LIM Settings Bits 91 Table 26 Interoperability of enabling/disabling methods vs. loading default values. 91 Table 27 Peak Short Circuit Detect Level Settings for Bits 94 Table 28 I2C Interface 118 Table 29 I2S Interface Timing 119 Table 30 - Interrupt Source Mapping 122 Table 31 Control Register Current Limit I_LIM Settings for Bits 128 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet PIN ASSIGNMENTS GPIO_TSC 124 GPIO4/CHRG_ILIM GPIO5/INT_OUT 001 GPIO6/ADC1 002 GPIO7/ADC3 GPIO8/ADC2 004 GPIO9/ADC0/MCLK_IN GPIO10 006 MIC_R- MIC_R+/DMICDAT2 008 MICBIAS_R/DMICSEL MICBIAS_L/DMICCLK 010 MIC_L+/DMICDAT1 MIC_L- 012 AFILT2 AFILT1 014 AGND_MIC AUDIO LISLP 016 LISLM LISRP 018 LISRM LLO_L 020 LLO_R AVREF 022 VDD_AUDIO33 ADC_REF 024 HP_R HP_L 026 AGND BYTE ORDERING AND OFFSET Most registers are defined within one byte width and occupy one byte in the address space. Some registers occupy more than one byte. Please refer to the individual register descriptions for information on how that register is stored in address space. REGISTER ACCESS TYPES TYPE RW R RW1C RW1A MEANING Readable and Writeable Read only Readable and Write 1 to this bit to clear it for interrupt status Readable and Write 1 to this bit to take actions RESERVED BIT FIELDS Bit fields and Bytes labeled RESERVED are reserved for future use. When writing to a register containing some RESERVED bits, the user should do a “read-modify-write” such that only the bits which are intended to be written are modified. DO NOT WRITE to registers containing all RESERVED bits. 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet AUDIO MODULE • 4 Channels 2 stereo DACs and 2 stereo ADCs with 24-bit resolution Supports full-duplex stereo audio Provides a mono output • 2.5W mono speaker amplifier 4 ohms and 5V • Stereo cap-less headphone amplifier • Two digital microphone inputs Mono or stereo operation Up to 4 microphones in a system • High performance analog mixer • 2 adjustable analog microphone bias outputs DESCRIPTION The audio system is a low power optimized, high fidelity, 4-channel audio codec with integrated Class D speaker amplifier, cap-less headphone amplifier. It provides high quality HD Audio capability for handheld applications. Figure 5 Audio Block Diagram AUDIO - PIN DEFINITIONS Pin # 007 008 009 010 011 PIN_ID MIC_RMIC_R+/DMICDAT2 MICBIAS_R/DMICSEL MICBIAS_L/DMICCLK MIC_L+/DMICDAT1 DESCRIPTION Differential Analog microphone negative input right channel Differential Analog microphone positive input right channel or second digital microphone data input Analog microphone supply right channel or digital microphone select output GPO Analog microphone supply left channel or digital microphone clock output Differential Analog microphone positive input left channel or first digital microphone data input 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet 012 MIC_L013 AFILT2 014 AFILT1 015 AGND_MIC 016 LISLP 017 LISLM 018 LISRP 019 LISRM 020 LLO_L 021 LLO_R 022 AVREF 023 VDD_AUDIO33 024 ADC_REF 025 HP_R 026 HP_L 027 AGND 028 VIRT_GND Differential Analog microphone negative input left channel ADC filter cap ADC filter cap Return path for microphone supply MICBIAS_L/R Differential Analog Line Level positive input left channel Differential Analog Line Level negative input left channel Differential Analog Line Level positive input right channel Differential Analog Line Level negative input right channel Single Ended Line Level Output Left channel Single Ended Line Level Output Right channel Analog reference virtual ground bypass cap Filter Capacitor for Internal 3.3V Audio LDO ADC reference bypass cap-less headphone output right channel Cap-less headphone output left channel Analog audio return Cap-less headphone signal return virtual ground AUDIO - SECTION OVERVIEW The Audio section can be divided into seven subsections. Analog Input Buffer & Converter Block DAC, ADC Audio Mixer Block Analog and Class D Output Blocks Sub System Control and Interface Blocks Note All register settings are lost when power is removed. AUDIO - ANALOG PERFORMANCE CHARACTERISTICS Unless otherwise specified, typical values at TA =25C, VSYS = 5V, TA = -40°C to +85°C, VCC_AUDIO33 = 3.3V, VDD_AUDIO18 = 1.8V, AGND = DGND = 0V, TA = 25 ° C 1 kHz input sine wave, Sample Frequency = 48 kHz, 0 dB = 1 VRMS into 10 KΩ PARAMETER Full Scale Input Voltage All Analog Inputs except Mic 0 dB gain Differential Mic Inputs +30dB gain Differentail Mic Inputs 0 dB gain Full Scale Output Voltage Line Input to Line Output HP Output PCM DAC to LINE_OUT Headphone output power Analog Frequency Response Digital S/N D/A PCM DAC to LINE_OUT A/D LINE_IN to PCM Dynamic Range -60dB signal level LINE_IN to LINE_OUT direct LINE_IN to LINE_OUT mixer LINE_IN to HP direct CONDITIONS MIN TYP MAX UNIT V rms mV rms V rms Per channel / 16 ohm load Per channel / 16 ohm load ORDERING INFORMATION Part / Order Number Shipping Packaging P95020ZLLG Tubes P95020ZLLG8 Tape and Reel P95020ZLLGI Tubes P95020ZLLGI8 Tape and Reel P95020ZNQG Tubes P95020NQG8 Tape and Reel P95020ZNQGI Tubes P95020ZNQGI8 Tape and Reel Package 124-pin LLGA 124-pin LLGA 124-pin LLGA 124-pin LLGA 132-pin QFN 132-pin QFN 132-pin QFN 132-pin QFN Temperature 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 2010 Integrated Device Technology, Inc. P95020 / Preliminary Datasheet Innovate with IDT. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support Corporate Headquarters Integrated Device Technology, Inc. 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.. Accelerated Thinking is a service mark of Int4grated Device Technology, Inc. All other brands, product names and marks are or may be trasdemarks or registered trademarks used to identify products or services of their respective owners.

PDF Datasheet Preview

Audio, Power Management and Control

P95020

Preliminary Datasheet

OVERVIEW

The P95020 is designed to provide maximum flexibility to system designers by providing full customization and programmability. It is the first of a new generation of standardized application-specific controllers that incorporates a general purpose microcontroller, a high fidelity audio CODEC including headphone outputs and a 2.5W Class D audio amplifier, full power management functionality, a touch screen controller and a real time clock all of which are required by portable consumer devices such as cellular phone handsets, portable gaming devices, digital media players, portable navigational devices, etc.

The general purpose microcontroller controls the device power-on/power-off sequencing and can also be used for general system housekeeping.

The P95020 includes two Interfaces, a master for communicating with an external EEPROM and a slave for communicating with the host.

The high fidelity audio CODEC along with headphone outputs and the watt Class D audio speaker amplifier comprise a total audio solution for portable applications.

The switch-mode EnergyPath Battery Charger operates with its own high efficiency buck regulator to transmit the watts available from a USB port to the system with minimal wasted power. It can also handle up to 2A from a wall charger.

Its power management features along with switch-mode converters and LDOs should be sufficient to provide power for even the most complex hand-held devices.

The integrated touch screen controller allows adding touch screen capability to devices at significantly reduced cost.

It also includes IDT‟s high quality, low power real time clock.

Smart Phones Portable Gaming Device Digital Media Players Portable Navigational Devices

KEY FEATURES

Quick Turn Customization Embedded Microcontroller

Master Controller during Power Up & Power-Down
• Initialization and power sequencing

Dynamic Power Management via bus interface Up to 10 General Purpose I/Os available General house keeping for P95020 and other devices Audio Features 4 Channel CODEC with 24-bit resolution and internal
registers for status and control Integrated Watt Mono Class D Amplifier
with Filterless Operation. Stereo cap-less headphone driver Differential Analog Audio Line Inputs Dual Mode Microphone Inputs Analog or DMIC Battery Charging Circuit Autonomous Li-Ion/Li-Poly charger up to 1.5A
• Automatic Load Prioritization
• Advanced Battery Safety features High efficiency switch-mode *EnergyPath controller USB or Wall-mounted Charging
• Programmable Current Limit
• Automatic end-of-charge control Internal 180 ideal diode with external ideal diode controller Power Management Features All Converters
• Power up/down sequence field reprogrammable with
external EEPROM
• Dynamic voltage scaling
• Host or I2C output enable / disable Buck DC-DC PWM converters with PFM mode
• Two at 500mA, 0.75V to 3.7V
• One at 1000mA, 0.75V to 3.7V Boost DC-DC converters
• One at A peak on inductor, 4.05V to 5.0V
• One LED supply with 2 W total output power

Two programmable current sinks, 25mA each Voltage limited to rating of external FET & diode Linear Regulators
• Three LDOs at 150mA, 0.75V to 3.7V
• Four LDOs at 50mA, 0.7V to 3.7V
• One always-on LDO at 10mA, or 3.0V ADC and Touch Screen Controller 4-wire touch screen interface One direct battery measurement channel One direct VSYS measurement channel One direct charge current measurement channel On-Chip temperature measurement Four auxiliary analog input channels shared with GPIO pins Touch pressure measurement Sample rate 62.5k SPS 12 bit resolution, DNL -1~+2 LSB, INL +-2 On-chip 2.5V reference
2010 Integrated Device Technology, Inc.

Pin MUX

P95020 / Preliminary Datasheet

BLOCK DIAGRAM

Thermal Sensor

Power-On-Reset SW_DET

Real Time Clock
10 GPIOs

ADC Touch Screen

Controller

LED_BOOST LED Backlight P/S with 2 Current Sinks

Hot Swap Switches

PLL &

Clock Synthesizer

I2C Slave I/F To

External Processor

Bus Arbitrator

Micro Controller
1.5K Byte Program
FUNCTIONAL MODES 19 REGISTER MAP 20 BYTE ORDERING AND OFFSET 21 REGISTER ACCESS TYPES 21 RESERVED BIT FIELDS 21 AUDIO MODULE 22 AUDIO - PIN 22 AUDIO - SECTION OVERVIEW 23 AUDIO - ANALOG PERFORMANCE CHARACTERISTICS 23 AUDIO - MICROPHONE INPUT PORT 24 AUDIO - ANALOG LINE 27 AUDIO - DAC, ADC 27 AUDIO - AUTOMATIC GAIN CONTROL 28 AUDIO - ANALOG MIXER BLOCK 28 AUDIO - DIGITAL AUDIO INPUT/OUTPUT INTERFACE 29 AUDIO - REFERENCE VOLTAGE GENERATOR, BUFFER, & FILTERING CAPS 31 AUDIO - ANALOG AND CLASS D OUTPUT BLOCK 31 AUDIO - CLASS-D BTL AMPLIFIER 32 AUDIO CLASS_D - REGISTERS 32 AUDIO CLASS_D - EQUALIZER COEFFICIENT & PRESCALER RAM EQRAM 39 AUDIO CONTROL REGISTERS 40 CHARGER MODULE 52 CHARGER - 52 CHARGER SUB-BLOCKS 52 CHARGER DC ELECTRICAL CHARACTERISTICS 53 CHARGER TYPICAL PERFORMANCE 54 CHARGER - REGISTER ADDRESSES 55 CHARGER - PRE-REGULATOR 58 IDEAL DIODE FROM VBAT TO VSYS 59 CHARGER - CHARGER/DISCHARGER 60 CHARGER - THERMAL MONITORING 60 CHARGER - POWER ON 60 CLOCK GENERATOR MODULE 61 CKGEN - PIN DEFINITIONS 61 CKGEN - OSCILLATOR CIRCUIT ELECTRICAL CHARACTERISTICS 62 CKGEN - PLL CONTROL 63 CKGEN OSCILLATOR CIRCUIT 63 CKGEN - CKGEN POWER SOURCE 63 CKGEN CLOCK 63 CKGEN CLOCK GENERATOR REGISTERS 64
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet

RTC MODULE 66 RTC - GENERAL 66 RTC - TIMEKEEPER REGISTERS 67 RTC - DATE REGISTERS 67 RTC - ALARM REGISTERS 68 RTC - INTERRUPT REGISTERS 69 RTC RESERVED REGISTERS 70

GENERAL PURPOSE 71 GENERAL PURPOSE TIMERS GENERAL 71 GENERAL PURPOSE TIMERS 71

DC_DC MODULE 74 2MHz, 500mA & 1000mA SYNCHRONOUS BUCK REGULATORS 75

BUCK1000 & BUCK500 - PIN 76 BUCK1000 & BUCK500 - ELECTRICAL CHARACTERISTICS 76 BUCK CONVERTERS TYPICAL PERFORMANCE 77 BUCK1000 & BUCK500 - REGISTER 79 BUCK1000 & BUCK500 - ENABLING & DISABLING 80 BUCK1000 & BUCK500 - APPLICATIONS INFORMATION 81 HIGH EFFICIENCY 10 LED BOOST CONVERTER AND SINKS 83 LED_BOOST - ELECTRICAL CHARACTERISTICS 84 LED_BOOST TYPICAL PERFORMANCE CHARACTERISTICS 84 LED_BOOST - REGISTER SETTINGS 85 LED_BOOST - ENABLING & DISABLING 86 LED_BOOST Over-Voltage Protection 87 LED_BOOST Over-Current 87 LED_BOOST - APPLICATIONS 87 BOOST5 1.5A, SYNCHRONOUS PWM BOOST CONVERTER 89 BOOST5 - ELECTRICAL 90 BOOST5 - REGISTER 90 BOOST5 - ENABLING & DISABLING 91 OUTPUT 92 BOOST5 - APPLICATIONS INFORMATION 92 CLASS_D BTL POWER OUTPUT STAGE 93 CLASS_D - ELECTRICAL CHARACTERISTICS 93 CLASS_D TYPICAL PERFORMANCE CHARACTERISTICS 94 CLASS_D REGISTER SETTINGS 94 CLASS_D - AUDIO INTERFACE AND DECODE 95 CLASS_D - SHORT CIRCUIT PROTECTION CIRCUITRY 95 CLASS_D - APPLICATIONS 95 TSC MODULE - ADC AND TOUCH SCREEN CONTROLLER 96 ADC AND TOUCH SCREEN CONTROLLER ELECTRICAL CHARACTERISTICS 97 ADC AND TOUCH SCREEN CONTROLLER PIN DEFINITIONS 97 ADC AND TOUCH SCREEN CONTROLLER 97 ADC AND TOUCH SCREEN CONTROLLER REGISTERS 100 PCON MODULE POWER CONTROLLER AND GENERAL PURPOSE I/O 107 GPIO PIN DEFINITIONS 107 POWER STATES 107 POWER SEQUENCING BY EMBEDDED 107 POWER ON RESET OUTPUT POR_OUT 108 POWER SWITCH DETECTOR 108 GPIO GENERAL DESCRIPTION 108 PCON 108 HOTSWAP 113 HOT SWAP LOAD SWITCHES ELECTRICAL 113 HOTSWAP TYPICAL PERFORMANCE CHARACTERISTICS 114 HOTSWAP PIN 115 PCON REGISTER - HOTSWAP CONFIGURATION 115 I2C_I2S MODULE 116 I2C_I2S - PIN 116 INTERRUPT DISPATCHER 117
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet
ACCESS ARBITER 117 DIGITAL AUDIO DATA SERIAL INTERFACE 117 I2C_I2S INTERFACE 118 GLOBAL REGISTER SETTINGS 0 120 ACCM REGISTERS 123 LDO MODULE 124 LDO - PIN DEFINITIONS 125 LDO - LDO_150 & LDO_050 ELECTRICAL CHARACTERISTICS 125 LDO TYPICAL PERFORMANCE CHARACTERISTICS 126 LDO - LDO_LP - ELECTRICAL 127 LDO - LIST OF ALL LDOS 127 LDO REGISTER SETTINGS 127 EMBUP EMBEDDED MICROCONTROLLER SUBSYSTEM & 131 FUNCTIONAL DESCRIPTION 131 ON-CHIP RAM & ROM 131 SLAVE INTERFACE 131 132 INTERRUPT 132 APPLICATIONS 133 EXTERNAL COMPONENTS 133 DIGITAL LOGIC DECOUPLING CAPACITORS 133 CLASS_D CONSIDERATIONS 133 SERIES TERMINATION RESISTORS 133 EXTERNAL RESISTOR CONNECTION 133 CRYSTAL LOAD CAPACITORS 133 PCB LAYOUT 133 POWER DISSIPATION AND THERMAL REQUIREMENTS 133 TYPICAL BLOCK PERFORMANCE CHARACTERISTICS GRAPHS 133 APPLICATIONS REFERENCE 134 SOLDERING 134 PACKAGE OUTLINE 134 LLG124 PACKAGE OUTLINE 134 NQG132 PACKAGE OUTLINE Exposed Die Paddle Size D2 = E2 = mm 135 ORDERING 135

TABLE OF FIGURES

Figure 1 P95020 Block Diagram. 2 Figure 2 P95020 Pinout Diagram LLG124 7 Figure 3 P95020 Pinout 8 Figure 4 Overall System Functional Diagram. 18 Figure 5 Audio Block Diagram 22 Figure 6 Digital Microphone Mode 3 26 Figure 7 Digital Microphone Mode 1 & 27 Figure 8 Automatic Gain 28 Figure 9 Charger Block Diagram 52 Figure 10 Pre-Regulator Efficiency vs Load Current VBUS = 5.0V, VSYS = 54 Figure Pre-Regulator Load Regulation VBUS = 5.0V, VSYS = 3.7V 55 Figure 12 Battery Charge Current vs Temperature 55 Figure 13 VSYS Regulation Curve Tracking VBAT 59 Figure 14 Clock Generator Block Diagram 61 Figure 15 DC_DC Block Diagram 74 Figure 16 BUCK500 / BUCK1000 Block Diagram 76 Figure 17 BUCK500 DC-DC Regulator Efficiency vs Load Current PWM Mode 78 Figure 18 BUCK1000 DC-DC Regulator Efficiency vs Load Current PWM Mode 78 Figure 19 BUCK500 DC-DC Regulator Efficiency vs Load Current PFM 79 Figure 20 BUCK500 or BUCK 1000 Applications Diagram 81 Figure 21 White LED Boost & Sink Driver Block Diagram 83
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet

Figure 22 LED Boost Efficiency vs Load Current two srings of 10 LEDs 84 Figure 23 LED Boost Efficiency vs VIN two srings of 10 LEDs 85 Figure 24 LED_BOOST Application 87 Figure 25 BOOST5 Block Diagram 89 Figure 26 BOOST5 Applications Diagram 92 Figure 27 Clss D BTL Efficiency vs Outpout Power 4 ohm speaker 94 Figure 28 ADC & Touchscreen Controller Block Diagram 96 Figure 29 Hotswap Block Diagram 113 Figure 30 Hotswap #1 ON Resistance vs Temperature 114 Figure 31 Hotswap #2 ON Resistance vs Temperature 114 Figure 32 I2C Read / Write Operation 117 Figure 33 LDO_050 / LDO_150 Block 124 Figure 34 LDO_050_n 50mA LDO Load Regulation 126 Figure 35 LDO_150_n 150mA LDO Load Regulation 126 Figure 36 - Top level Interrupt 132 Figure 37 Power Derating Curve 133

LIST OF TABLES

Table 1 LLG124 Pin Functions by Pin Number See Figure 2 9 Table 2 - NQG132 Pin Functions by Pin Number see Figure 3 11 Table 3 Register Address Global Mapping 20 Table 4 - Valid Digital Mic Configurations 25 Table 5 - MCLK Rate selection MCLK_DIV2 MCLK_RATE 29 Table 6 MCLK/Sample Rate 30 Table 7 - EQRAM 39 Table 8 Register 0xA090 0x90 Current Limit I_LIM Settings Bits [2:0] 56 Table 9 Register 0xA091, 0x91 Charging Maximum Voltage CHG_VOL Settings, Bits 56 Table 10 Register 0xA091, 0x91 Charging Current Limit via Sense Resistor CHG_CUR Settings, Bits [3:0] 56 Table 11 Register 0xA092 0x92 Charging Termination Time CHG_TERM Settings Bits [1:0] 56 Table 12 Register 0xA093 0x93 Battery Recovery Charge Current Control Settings Bits 57 Table 13 Register 0xA093, 0x93 Battery Good Voltage Threshold Settings, Bits [4:3] 57 Table 14 Register 0xA095, 0x95 Current Charger Mode Settings, Bits [4:3] 57 Table 15 - Crystal 63 Table 16 - Alarm mask bits 66 Table 17 DC-DC Block Registers Including the CLASS_D BTL Power 74 Table 18 BUCK500_0, BUCK500_1 and BUCK1000 Register Addresses 79 Table 19 Output Voltage Register Settings, Bits [6:0] 79 Table 20 Control Register Cycle by Cycle Current Limit I_LIM Settings for Bits [3:2] [Note ] 80 Table 21 Interoperability of enabling/disabling methods vs. loading default values. 80 Table 22 Register 0xA086 0x86 IOUT Current Settings for Bits [4:0], Half Scale and Full Scale................................... 85 Table 23 Interoperability of enabling/disabling methods vs. loading default values. 86 Table 24 Register 0xA088 Output Voltage Bit Setting [4:0] 90 Table 25 Register 0xA089 0x89 Peak Current Limit I_LIM Settings Bits 91 Table 26 Interoperability of enabling/disabling methods vs. loading default values. 91 Table 27 Peak Short Circuit Detect Level Settings for Bits 94 Table 28 I2C Interface 118 Table 29 I2S Interface Timing 119 Table 30 - Interrupt Source Mapping 122 Table 31 Control Register Current Limit I_LIM Settings for Bits 128
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet

PIN ASSIGNMENTS

GPIO_TSC
124 GPIO4/CHRG_ILIM

GPIO5/INT_OUT 001

GPIO6/ADC1 002

GPIO7/ADC3

GPIO8/ADC2 004

GPIO9/ADC0/MCLK_IN

GPIO10 006

MIC_R-

MIC_R+/DMICDAT2 008

MICBIAS_R/DMICSEL

MICBIAS_L/DMICCLK 010

MIC_L+/DMICDAT1

MIC_L- 012

AFILT2

AFILT1 014

AGND_MIC

AUDIO

LISLP 016

LISLM

LISRP 018

LISRM

LLO_L 020

LLO_R

AVREF 022

VDD_AUDIO33

ADC_REF 024

HP_R

HP_L 026

AGND
BYTE ORDERING AND OFFSET

Most registers are defined within one byte width and occupy one byte in the address space. Some registers occupy more than one byte. Please refer to the individual register descriptions for information on how that register is stored in address space.

REGISTER ACCESS TYPES

TYPE RW R RW1C RW1A

MEANING Readable and Writeable Read only Readable and Write 1 to this bit to clear it for interrupt status Readable and Write 1 to this bit to take actions

RESERVED BIT FIELDS

Bit fields and Bytes labeled RESERVED are reserved for future use. When writing to a register containing some RESERVED bits, the user should do a “read-modify-write” such that only the bits which are intended to be written are modified.

DO NOT WRITE to registers containing all RESERVED bits.
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet

AUDIO MODULE
• 4 Channels 2 stereo DACs and 2 stereo ADCs with 24-bit
resolution Supports full-duplex stereo audio Provides a mono output
• 2.5W mono speaker amplifier 4 ohms and 5V
• Stereo cap-less headphone amplifier
• Two digital microphone inputs

Mono or stereo operation Up to 4 microphones in a system
• High performance analog mixer
• 2 adjustable analog microphone bias outputs

DESCRIPTION The audio system is a low power optimized, high fidelity, 4-channel audio codec with integrated Class D speaker amplifier, cap-less headphone amplifier. It provides high quality HD Audio capability for handheld applications.

Figure 5 Audio Block Diagram

AUDIO - PIN DEFINITIONS

Pin # 007 008 009 010 011

PIN_ID MIC_RMIC_R+/DMICDAT2 MICBIAS_R/DMICSEL MICBIAS_L/DMICCLK MIC_L+/DMICDAT1

DESCRIPTION Differential Analog microphone negative input right channel Differential Analog microphone positive input right channel or second digital microphone data input Analog microphone supply right channel or digital microphone select output GPO Analog microphone supply left channel or digital microphone clock output Differential Analog microphone positive input left channel or first digital microphone data input
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet
012 MIC_L013 AFILT2 014 AFILT1 015 AGND_MIC 016 LISLP 017 LISLM 018 LISRP 019 LISRM 020 LLO_L 021 LLO_R 022 AVREF 023 VDD_AUDIO33 024 ADC_REF 025 HP_R 026 HP_L 027 AGND 028 VIRT_GND

Differential Analog microphone negative input left channel ADC filter cap ADC filter cap Return path for microphone supply MICBIAS_L/R Differential Analog Line Level positive input left channel Differential Analog Line Level negative input left channel Differential Analog Line Level positive input right channel Differential Analog Line Level negative input right channel Single Ended Line Level Output Left channel Single Ended Line Level Output Right channel Analog reference virtual ground bypass cap Filter Capacitor for Internal 3.3V Audio LDO ADC reference bypass cap-less headphone output right channel Cap-less headphone output left channel Analog audio return Cap-less headphone signal return virtual ground

AUDIO - SECTION OVERVIEW

The Audio section can be divided into seven subsections.

Analog Input Buffer & Converter Block DAC, ADC Audio Mixer Block Analog and Class D Output Blocks Sub System Control and Interface Blocks Note All register settings are lost when power is removed.

AUDIO - ANALOG PERFORMANCE CHARACTERISTICS

Unless otherwise specified, typical values at TA =25C, VSYS = 5V, TA = -40°C to +85°C, VCC_AUDIO33 = 3.3V, VDD_AUDIO18 = 1.8V, AGND = DGND = 0V, TA = 25 ° C 1 kHz input sine wave, Sample Frequency = 48 kHz, 0 dB = 1 VRMS into 10 KΩ

PARAMETER Full Scale Input Voltage All Analog Inputs except Mic 0 dB gain Differential Mic Inputs +30dB gain Differentail Mic Inputs 0 dB gain Full Scale Output Voltage Line Input to Line Output HP Output PCM DAC to LINE_OUT Headphone output power Analog Frequency Response

Digital S/N

D/A PCM DAC to LINE_OUT A/D LINE_IN to PCM Dynamic Range -60dB signal level LINE_IN to LINE_OUT direct LINE_IN to LINE_OUT mixer LINE_IN to HP direct

CONDITIONS

MIN TYP MAX UNIT

V rms
mV rms

V rms

Per channel / 16 ohm load

Per channel / 16 ohm load
ORDERING INFORMATION

Part / Order Number Shipping Packaging

P95020ZLLG

Tubes

P95020ZLLG8

Tape and Reel

P95020ZLLGI

Tubes

P95020ZLLGI8

Tape and Reel

P95020ZNQG

Tubes

P95020NQG8

Tape and Reel

P95020ZNQGI

Tubes

P95020ZNQGI8

Tape and Reel

Package
124-pin LLGA 124-pin LLGA 124-pin LLGA 124-pin LLGA 132-pin QFN 132-pin QFN 132-pin QFN 132-pin QFN

Temperature
0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
2010 Integrated Device Technology, Inc.

P95020 / Preliminary Datasheet

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2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.. Accelerated Thinking is a service mark of Int4grated Device Technology, Inc. All other brands, product names and marks are or may be trasdemarks or registered trademarks used to identify products or services of their respective owners.

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Datasheet ID: P95020ZNQG8 637503