HSDCEP

HSDCEP Datasheet

High-Speed Data Converter Evaluation Platform HSDCEP User Guide

Part	Datasheet
HSDCEP	HSDCEP (pdf)

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High-Speed Data Converter Evaluation Platform HSDCEP User Guide Evaluates RF-DACs > 1.5Gsps and DUCs The high-speed data converter evaluation platform HSDCEP is a PC-based platform that provides a comprehensive tool for evaluating Maxim’s RF digitalto-analog converters RF-DACs that have update rates R 1.5Gsps and Maxim’s digital upconverters DUCs . The HSDCEP generates test patterns at rates of up to 1.25Gbps per data pin pair, on up to four parallel 16-bit LVDS buses. A data pattern with a maximum length of 64 mega-words Mw , with each word being 16 bits wide, can be uploaded to the HSDCEP memory over a USB port. The HSDCEP uses a highspeed XilinxM VirtexM-5 FPGA to play back the data pattern to the DAC or DUC under evaluation. The HSDCEP operates from a single 5V, 6A supply. The HSDCEP software runs on PCs using the Windows XPM SP2 or later operating system with a USB port. Ordering Information appears at end of data sheet. S Evaluates Maxim RF-DACs > 1.5Gsps and DUCs S Four Parallel 16-Bit Output Buses LVDS S Eight Clock-Capable Ports LVDS S Output Rate Up to 1.25Gwps LVDS Per Output Bus S 64M x 16-Bit Words Pattern Storage S FPGA Configuration Stored on the PC and Downloaded Through the USB Port S USB Communication 480Mbps S Single 5V Supply Operation Power Supply Included S LEDs to Display DUT and FPGA Status S Simple Command-Prompt Software Interface Enables Scripting to Run Command Sequences S FPGA Temperature Monitoring 5VDC1 HIGH-SPEED DATA CONVERTER EVALUATION PLATFORM HSDCEP POWERSUPPLY CONN. SW1 USB RESET 32Mb x 64 DDR2 32Mb x 64 DDR2 32Mb x 64 DDR2 32Mb x 64 DDR2 J5/J6 SDRAM SDRAM SDRAM SDRAM PC4200 PC4200 PC4200 PC4200 DDR2 SDRAM CONTROL GPIF CONN. CONTROLLER DATA INTERFACE CONTROL REGISTER ASYNCHRONOUS FIFOs READ AND WRITE 64x OUTPUT A CLOCK B ASYNCHRONOUS FIFO D 63:0 INPUT CLOCK CLOCK DISTRIBUTION FPGA RESET FIFO CONTROL Xilinx Virtex-5 FPGA STATUS LEDs XTAL OSC WINDOWS XP PATTERN GENERATION AND FORMATTING TOOLS For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at High-Speed Data Converter Evaluation Platform HSDCEP User Guide Evaluates RF-DACs > 1.5Gsps and DUCs Absolute Maximum Ratings 5.5V Continuous Power Dissipation TA = +25°C ........................33W Operating Temperature Range.............................. 0°C to +35°C Storage Temperature Range............................. -60°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics 5VDC1 = 5V, data output word rate = 4.6Gwps. PARAMETER Minimum DATACLK Rate Maximum DATACLK Rate Maximum Output Word Rate Output Bus Width Pattern Length Pattern Block Resolution SYMBOL 4 port CONDITIONS MIN TYP MAX UNITS 120 MHz Gwps Bits 64M Words Words Output Data Jitter Supply Voltage Range Supply Current 5VDC1 Note 1 psP-P Note 1 HSDCEP-powered, Maxim-supplied FPGA firmware loaded, and active heat sink operating. Table Board Connector and Switch Description DESIGNATION 5VDC1 J1 J2, J3, J5, J6 SW1 SW4 DESCRIPTION External 5.0V power-supply connection. Connect a 5V, 6A power supply to this connector. USB port. Do not future use. High-speed output bus connector. The pinout of this connector is EV Kit/FPGA-firmware specific. USB communications reset. FPGA reset. Memory patterns must be reloaded after reset. Maxim Integrated 2 High-Speed Data Converter Evaluation Platform HSDCEP User Guide Evaluates RF-DACs > 1.5Gsps and DUCs J4 5VDC1 POWER J1 USB TYPE ‘B’ J2 OFF BOARD SPI INTERFACE EV KIT MOUNTING INTERFACE JTAG EV KIT MOUNTING FPGA INDICATOR LEDS J13 PARALLEL BUS Ordering Information TEMP RANGE 0°C to +35°C PIN-PACKAGE BOARD Maxim Integrated 9 High-Speed Data Converter Evaluation Platform HSDCEP User Guide Evaluates RF-DACs > 1.5Gsps and DUCs 12/12 Initial release PAGES CHANGED Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 2012 Maxim Integrated Products, Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

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High-Speed Data Converter Evaluation Platform HSDCEP User Guide

Evaluates RF-DACs > 1.5Gsps and DUCs

The high-speed data converter evaluation platform HSDCEP is a PC-based platform that provides a comprehensive tool for evaluating Maxim’s RF digitalto-analog converters RF-DACs that have update rates R 1.5Gsps and Maxim’s digital upconverters DUCs . The HSDCEP generates test patterns at rates of up to 1.25Gbps per data pin pair, on up to four parallel 16-bit LVDS buses. A data pattern with a maximum length of 64 mega-words Mw , with each word being 16 bits wide, can be uploaded to the HSDCEP memory over a USB port. The HSDCEP uses a highspeed XilinxM VirtexM-5 FPGA to play back the data pattern to the DAC or DUC under evaluation.

The HSDCEP operates from a single 5V, 6A supply.

The HSDCEP software runs on PCs using the Windows XPM SP2 or later operating system with a USB port.
Ordering Information appears at end of data sheet.

S Evaluates Maxim RF-DACs > 1.5Gsps and DUCs S Four Parallel 16-Bit Output Buses LVDS S Eight Clock-Capable Ports LVDS S Output Rate Up to 1.25Gwps LVDS Per Output Bus S 64M x 16-Bit Words Pattern Storage S FPGA Configuration Stored on the PC and

Downloaded Through the USB Port S USB Communication 480Mbps S Single 5V Supply Operation Power Supply

Included S LEDs to Display DUT and FPGA Status S Simple Command-Prompt Software Interface

Enables Scripting to Run Command Sequences S FPGA Temperature Monitoring
5VDC1

HIGH-SPEED DATA CONVERTER EVALUATION PLATFORM HSDCEP

POWERSUPPLY CONN.

SW1 USB RESET
32Mb x 64 DDR2 32Mb x 64 DDR2 32Mb x 64 DDR2 32Mb x 64 DDR2

J5/J6

SDRAM

SDRAM

SDRAM

SDRAM

PC4200

PC4200

PC4200

PC4200

DDR2 SDRAM CONTROL

GPIF

CONN.

CONTROLLER

DATA INTERFACE

CONTROL REGISTER

ASYNCHRONOUS FIFOs

READ AND WRITE
64x OUTPUT A CLOCK

B ASYNCHRONOUS

FIFO

D 63:0

INPUT

CLOCK

CLOCK DISTRIBUTION

FPGA RESET

FIFO CONTROL

Xilinx Virtex-5 FPGA

STATUS LEDs

XTAL OSC

WINDOWS XP

PATTERN GENERATION AND FORMATTING TOOLS
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at

High-Speed Data Converter Evaluation Platform HSDCEP User Guide

Evaluates RF-DACs > 1.5Gsps and DUCs

Absolute Maximum Ratings
5.5V Continuous Power Dissipation TA = +25°C ........................33W

Operating Temperature Range.............................. 0°C to +35°C Storage Temperature Range............................. -60°C to +125°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics
5VDC1 = 5V, data output word rate = 4.6Gwps.

PARAMETER Minimum DATACLK Rate Maximum DATACLK Rate Maximum Output Word Rate Output Bus Width Pattern Length Pattern Block Resolution

SYMBOL 4 port

CONDITIONS

MIN TYP MAX UNITS
120 MHz

Gwps

Bits
64M Words

Words

Output Data Jitter Supply Voltage Range Supply Current
5VDC1

Note 1
psP-P

Note 1 HSDCEP-powered, Maxim-supplied FPGA firmware loaded, and active heat sink operating.

Table Board Connector and Switch Description

DESIGNATION 5VDC1 J1

J2, J3, J5, J6 SW1 SW4

DESCRIPTION External 5.0V power-supply connection. Connect a 5V, 6A power supply to this connector. USB port. Do not future use. High-speed output bus connector. The pinout of this connector is EV Kit/FPGA-firmware specific. USB communications reset. FPGA reset. Memory patterns must be reloaded after reset.

Maxim Integrated
2

High-Speed Data Converter Evaluation Platform HSDCEP User Guide

Evaluates RF-DACs > 1.5Gsps and DUCs

J4 5VDC1 POWER

J1 USB TYPE ‘B’

J2 OFF BOARD SPI INTERFACE

EV KIT MOUNTING

INTERFACE

JTAG

EV KIT

MOUNTING

FPGA INDICATOR LEDS

J13 PARALLEL BUS
Ordering Information

TEMP RANGE 0°C to +35°C

PIN-PACKAGE BOARD

Maxim Integrated
9

High-Speed Data Converter Evaluation Platform HSDCEP User Guide

Evaluates RF-DACs > 1.5Gsps and DUCs
12/12

Initial release

PAGES CHANGED

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA
2012 Maxim Integrated Products,

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived HSDCEP Datasheet file may be downloaded here without warranties.

Datasheet ID: HSDCEP 647198