M2041-12-622.0800

M2041-12-622.0800 Datasheet

M2041

Part	Datasheet
M2041-12-622.0800	M2041-12-622.0800 (pdf)

Related Parts	Information
M2041-13-622.0800	M2041-13-622.0800
M2041-11-622.0800	M2041-11-622.0800
M2041-13-622.0800T	M2041-13-622.0800T
M2041-12-622.0800T	M2041-12-622.0800T
M2041-11-622.0800T	M2041-11-622.0800T

PDF Datasheet Preview
Integrated Circuit Systems, Inc. M2041 VCSO BASED CLOCK PLL WITH AUTOSWITCH The M2041 is a VCSO Voltage Controlled SAW Oscillator based clock generator PLL. It is designed for clock protection, frequency translation and jitter attenuation in optical networking systems supporting 2.5-10Gb data rates. It features dual differential inputs with two modes of input selection manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response. • Integrated SAW surface acoustic wave delay line; output frequencies of 125 to 700 MHz;* outputs VCSO frequency or 1/4 pin-configurable dividers • Loss of Lock LOL indicator output • Narrow Bandwidth control input NBW pin ; Initialization INIT input overrides NBW at power-up • Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL • AutoSwitch AUTO pin - automatic non-revertive reference clock reselection upon clock failure Hitless Switching HS options with or without Phase Build-out PBO enable SONET GR-253 /SDH G.813 MTIE and TDEV compliance • Acknowledge pin REF_ACK pin indicates the actively selected reference input • Dual differential LVPECL outputs • Low phase jitter of < 0.5ps rms, typical 12kHz to 20MHz or 50kHz to 80MHz • Single 3.3V power supply • Small 9 x 9 mm SMT surface mount package SIMPLIFIED BLOCK DIAGRAM PIN ASSIGNMENT 9 x 9 mm SMT nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 AUTO FIN_SEL1 FIN_SEL0 MR_SEL REF_ACK LOL NBW VCC DNC M2041 Top View P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND nOP_IN OP_OUT nOP_OUT OP_IN Example I/O Clock Frequency Combinations Using M2041-11-622.0800 Input Reference Clock MHz PLL Ratio

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

M2041

VCSO BASED CLOCK PLL WITH AUTOSWITCH

The M2041 is a VCSO Voltage Controlled SAW Oscillator based clock generator PLL. It is designed for clock protection, frequency translation and jitter attenuation in optical networking systems supporting 2.5-10Gb data rates. It features dual differential inputs with two modes of input selection manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response.
• Integrated SAW surface acoustic wave delay line;
output frequencies of 125 to 700 MHz;* outputs VCSO frequency or 1/4 pin-configurable dividers
• Loss of Lock LOL indicator output
• Narrow Bandwidth control input NBW pin ;

Initialization INIT input overrides NBW at power-up
• Dual reference clock inputs support LVDS, LVPECL,

LVCMOS, LVTTL
• AutoSwitch AUTO pin - automatic non-revertive
reference clock reselection upon clock failure Hitless Switching HS options with or without Phase Build-out PBO enable SONET GR-253 /SDH G.813 MTIE and TDEV compliance
• Acknowledge pin REF_ACK pin indicates the actively
selected reference input
• Dual differential LVPECL outputs
• Low phase jitter of < 0.5ps rms, typical
12kHz to 20MHz or 50kHz to 80MHz
• Single 3.3V power supply
• Small 9 x 9 mm SMT surface mount package

SIMPLIFIED BLOCK DIAGRAM

PIN ASSIGNMENT 9 x 9 mm SMT
nDIF_REF1

DIF_REF1

REF_SEL
nDIF_REF0

DIF_REF0

AUTO

FIN_SEL1

FIN_SEL0 MR_SEL

REF_ACK LOL NBW VCC DNC

M2041

Top View

P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
nOP_IN

OP_OUT
nOP_OUT

OP_IN

Example I/O Clock Frequency Combinations Using M2041-11-622.0800

Input Reference Clock MHz

PLL Ratio

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Datasheet ID: M2041-12-622.0800 637420