IDTCV123PV8

IDTCV123PV8 Datasheet

IDTCV123 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Part	Datasheet
IDTCV123PV8	IDTCV123PV8 (pdf)

Related Parts	Information
IDTCV123PVG8	IDTCV123PVG8
IDTCV123PVG	IDTCV123PVG
IDTCV123PV	IDTCV123PV

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IDTCV123 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR IDTCV123 FEATURES: • One high precision PLL for CPU, with SSC and N programmable • One high precision PLL for SRC/PCI/SATA, SSC and N programmable • One high precision PLL for 96MHz/48MHz • Band-gap circuit for differential outputs • Supports spread spectrum modulation, down spread • Supports SMBus block read/write, index read/write • Selectable output strength for REF • Allows for CPU frequency to change to a higher frequency for maximum system computing power • Available in SSOP package OUTPUTS: • 20.7V current differential CPU CLK pair • 80.7V current differential SRC CLK pair, one dedicated for SATA • One CPU_ITP/SRC selectable CLK pair • 8PCI, 3 free running, 33.3MHz • 196MHz,148MHz • 2REF DESCRIPTION: IDTCV123 is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. KEY SPECIFICATION: • CPU/SRC CLK cycle to cycle jitter < 85ps • SATA CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 250ps • Static PLL frequency divide error < 114 ppm • Static PLL frequency divide error for 48MHz < 5 ppm FUNCTIONAL BLOCK DIAGRAM X1 X2 SDATA SCLK XTAL Osc Amp SM Bus Controller VTT_PWRGD#/PD FSA.B.C Control Logic PLL1 SSC N Programmable CPU CLK Output Buffers Stop Logic IREF ITP_EN PLL2 SSC N Programmable SRC CLK Output Buffer Stop Logic IREF PLL3 48MHz/96MHz Output BUffer The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 2004 Integrated Device Technology, Inc. CPU[1:0] CPU_ITP/SRC6 REF[0:1] SRC[6:0] SATA_SRC PCI[5:0], PCIF[2:0] 48MHz DOT96 ORDERING INFORMATION IDTCV XXX Device Type Package X Grade COMMERCIAL TEMPERATURE RANGE Blank Commercial Temperature Range 0°C to +70°C PV Small Shrink Outline Package PVG SSOP - Green 123 Programmable FlexPC Clock for P4 Processor CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

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IDTCV123 PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

IDTCV123

FEATURES:
• One high precision PLL for CPU, with SSC and N programmable
• One high precision PLL for SRC/PCI/SATA, SSC and N programmable
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Supports spread spectrum modulation, down spread
• Supports SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a higher frequency for
maximum system computing power
• Available in SSOP package

OUTPUTS:
• 2*0.7V current differential CPU CLK pair
• 8*0.7V current differential SRC CLK pair, one dedicated
for SATA
• One CPU_ITP/SRC selectable CLK pair
• 8*PCI, 3 free running, 33.3MHz
• 1*96MHz,1*48MHz
• 2*REF

DESCRIPTION:

IDTCV123 is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance.

Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups.

KEY SPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error < 114 ppm
• Static PLL frequency divide error for 48MHz < 5 ppm

FUNCTIONAL BLOCK DIAGRAM

X1 X2

SDATA SCLK

XTAL Osc Amp

SM Bus Controller

VTT_PWRGD#/PD FSA.B.C

Control Logic

PLL1 SSC N Programmable

CPU CLK Output Buffers

Stop Logic

IREF

ITP_EN

PLL2 SSC N Programmable

SRC CLK Output Buffer

Stop Logic

IREF

PLL3
48MHz/96MHz Output BUffer

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
2004 Integrated Device Technology, Inc.

CPU[1:0] CPU_ITP/SRC6 REF[0:1]

SRC[6:0] SATA_SRC PCI[5:0], PCIF[2:0]
48MHz DOT96
ORDERING INFORMATION

IDTCV XXX

Device Type Package

X Grade

COMMERCIAL TEMPERATURE RANGE

Blank Commercial Temperature Range 0°C to +70°C

PV Small Shrink Outline Package PVG SSOP - Green 123 Programmable FlexPC Clock for

P4 Processor

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDTCV123PV8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDTCV123PV8 637403