IDT74LVC16501APAG
IDT74LVC16501APAG Datasheet
IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
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IDT74LVC16501APAG |
IDT74LVC16501APAG (pdf) |
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| IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE IDT74LVC16501A FEATURES: • Typical tSK o Output Skew < 250ps • ESD > 2000V per MIL-STD-883, Method 3015 > 200V using machine model C = 200pF, R = 0 • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels W typ. static • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP and TSSOP packages DRIVE FEATURES: • High Output Drivers ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DESCRIPTION: The LVC16501A is built using advanced dual metal CMOS technology. This high-speed, low power 18-bit registered bus transceiver combines Dtype latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by outputenable OEAB and OEBA , latch enable LEAB and LEBA and clock CLKAB and CLKBA inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar but requires using OEBA, LEBA and CLKBA. Flowthrough organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The LVC16501A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. FUNCTIONAL BLOCK DIAGRAM OEAB 1 CLKBA 30 LEBA 28 OEBA 27 CLKAB 55 LEAB 2 TO 17 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 2006 Integrated Device Technology, Inc. JUNE 2006 DSC-4481/6 IDT74LVC16501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER PIN CONFIGURATION OEAB LEAB OEBA LEBA CLKAB 46 GND CLKBA SSOP/ TSSOP TOP VIEW INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS 1 Unit VTERM Terminal Voltage with Respect to GND to TSTG Storage Temperature ORDERING INFORMATION IDT XX LVC X XXXX Temp. Range Bus-Hold Family Device Type Package INDUSTRIAL TEMPERATURE RANGE PV PVG PA PAG Shrink Small Outline Package SSOP - Green Thin Shrink Small Outline Package TSSOP - GREEN 501A 18-Bit Registered Transceiver with 3 State Outputs Double-Density, ±24mA Blank No Bus-hold -40°C to +85°C CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support: |
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