M25P40-VMP6G

M25P40-VMP6G Datasheet

Forté Serial Flash Memory M25P40

Part	Datasheet
M25P40-VMP6G	M25P40-VMP6G (pdf)

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PDF Datasheet Preview
Forté Serial Flash Memory M25P40 4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface - 4 Mbit of Flash memory - V to V single supply voltage - SPI bus compatible serial interface - 75 MHz clock rate maximum - Page Program up to 256 bytes in ms typical - Sector Erase 512 Kbit in s typical - Bulk Erase 4 Mbit in s typical - Deep Power-down mode 1 µA typical - Hardware Write Protection protected area size defined by three non-volatile bits BP0, BP1 and BP2 - Electronic signatures JEDEC standard two-byte signature 2013h Unique ID code UID with 16 bytes read- only, available upon customer request RES instruction, one-byte, signature 12h , for backward compatibility - Packages RoHS compliant - Automotive grade parts available SO8 MN 150 mils width DFN8 MS MLP8 6 x 5 mm UFDFPN8 MB MLP8 2 x 3 mm SO8W MW 208 mils width VFDFPN8 MP MLP8 6 x 5 mm UFDFPN8 MC MLP8 4 x 3 mm April 2010 1/61 Contents Contents M25P40 Description 6 Signal description 8 Serial Data output Q 8 Serial Data input D 8 Serial Clock C 8 Chip Select S 8 Hold 8 Write Protect W 8 VCC supply voltage 9 VSS ground 9 SPI modes 10 Operating features 12 Page Programming 12 Sector Erase and Bulk Erase 12 Polling during a Write, Program or Erase cycle 12 Active Power, Standby Power and Deep Power-down modes 12 Status Register 13 Protection modes 13 Hold condition 14 Memory organization 16 Instructions 18 Write Enable WREN 19 Ordering Information, Standard Parts 55 Ordering Information, Automotive Parts 57 3/61 List of tables List of tables M25P40 Table Table Table Table Table Table 4/61 M25P40 List of figures List of figures Figure Logic diagram 6 Figure SO and MLP8 connections 7 Figure Bus Master and memory devices on the SPI bus 10 Figure SPI modes supported 11 Figure Hold condition activation 15 Figure Block diagram 17 Figure Write Enable WREN instruction sequence 19 Figure Write Disable WRDI instruction sequence 20 Figure Read Identification RDID instruction sequence and data-out sequence 22 Figure Read Status Register RDSR instruction sequence and data-out sequence 23 Figure Write Status Register WRSR instruction sequence 24 Figure Read Data Bytes READ instruction sequence and data-out sequence 26 Figure Read Data Bytes at Higher Speed FAST_READ instruction sequence and data-out sequence 28 Figure Page Program PP instruction sequence 29 Figure Sector Erase SE instruction sequence 30 Figure Bulk Erase BE instruction sequence 31 Figure Deep Power-down DP instruction sequence 32 Figure Release from Deep Power-down and Read Electronic Signature RES instruction sequence and data-out sequence 34 Figure Release from Deep Power-down instruction sequence 34 Figure Power-up timing 36 Figure AC measurement I/O waveform 41 Figure Serial input timing 46 Figure Write Protect setup and hold timing during WRSR when SRWD = 1 46 Figure Hold timing 47 Figure Output timing 47 Figure SO8 narrow 8 lead plastic Small Outline, 150 mils body width, package outline. 48 Figure SO8W 8 lead plastic small outline, 208 mils body width, package outline. 49 Figure DFN8 MLP8 8-lead, dual flat package no lead, 6 x 5 mm, package outline 50 Figure VFDFPN8 MLP8 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 x 5 mm, package outline 51 Figure UFDFPN8 MLP8 8-lead ultra thin fine pitch dual flat package no lead, 4 x 3 mm package mechanical data52 Figure UFDFPN8 MLP8 8-lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package outline54 5/61 M25P40 The M25P40 is a 4 Mbit 512 K x 8 Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25P40 features high performance instructions allowing clock frequency up to 75 MHz. 1 The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. In order to meet environmental requirements, Numonyx offers the M25P40 in RoHS compliant packages, which are Lead-free. RoHS specifications are available at: Important: This datasheet details the functionality of the M25P40 devices, based on the previous 150 nm process or based on the current 110 nm process available since August The new device in the 110 nm process has the following additional features and is completely backward compatible with the old one in 150 nm: - improved max frequency Fast Read to 75 MHz in the standard Vcc range V to V, while the max frequency Fast Read in the extended Vcc range V to V is 40 MHz - UID/CFD protection feature Figure Logic diagram VCC D C S W HOLD Q M25P40 AI04090 6/61 75 MHz operation is available only on the VCC range V - V and for 110 nm process technology devices, identified by process identification digit "4" in the device marking and process letter "B" in the part number. M25P40 Table Signal names Signal name Function C D Q S W HOLD VCC VSS Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Figure SO and MLP8 connections Direction Input Output Input M25P40 S1 Q2 8 VCC 7 HOLD VSS 4 AI04091B There is an exposed central pad on the underside of the MLP8 packages. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. See Section 11 Package mechanical for package dimensions, and how to identify pin-1. 7/61 Details of how to find the technology process in the marking are given in AN1995, see also Section 12 Ordering Information, Standard Parts. 75 MHz operation is available only on the VCC range V - V the maximum frequency in the extended Vcc range V to V is 40 MHz. Typical values given for TA = 25 °C. tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production. Expressed as a slew-rate. Only applicable as a constraint for a WRSR instruction when SRWD is set at Figure Serial input timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX tCLCH MSB IN LSB IN High Impedance Q Figure Write Protect setup and hold timing during WRSR when SRWD = 1 W tWHSL tSHWL High Impedance Q AI07439 46/61 M25P40 Figure Hold timing tCHHL tHLQZ HOLD Figure Output timing C tCLQV tCLQX Q tCLQX tCLQV ADDR. D LSB IN DC and AC parameters tHLCH tCHHH tHHCH tHHQX AI02032 tSHQZ tQLQH tQHQL LSB OUT Ordering Information, Standard Parts 12 Ordering Information, Standard Parts Table Ordering information scheme Example:M25P40 V MN 6 T Device Type M25P = Serial Flash memory for code storage Device Function 40 = 4 Mbit 512 K x 8 Security features 1 = no extra security S = CFD programmed with UID Operating Voltage V = VCC = V to V Package 2 MN = SO8N 150 mil width MP = VFDFPN8 6 x 5 mm MLP8 MW = SO8W 208 mils width MS = DFN8 MLP8 2 , 6 x 5 mm MB = UFDFPN8 MLP8 , 2 x 3 mm MC = UFDFPN8 MLP8 , 4 x 3 mm Device grade 6 = Industrial temperature range, to 85 °C. Device tested with standard test flow. 3 = Automotive temperature range to 125 °C . Device tested with High Reliability Certified Flow. 4 Option blank = Standard Packing T = Tape and Reel Packing Plating technology P or G = RoHS compliant Lithography 5 /X = 150 nm technology /4 = 110 nm, Catania Diffusion Plant B = 110 nm , Fab 2 Diffusion Plant Automotive Grade A 4 = Automotive part to 125 °C . Device tested with High Reliability Certified Flow 3 Secure options are available upon customer request. Exposed pad of 3 x 3 mm. Device grade 3 available in an SO8 RoHS compliant package. Numonyx strongly recommends the use of the Automotive Grade devices Autograde 6 and grade 3 for use in an automotive environment. The High Reliability Certified Flow HRCF is described in the quality note QNEE9801. Please ask your nearest Numonyx sales office for a copy. The letter /X denotes the automotive grade 3 device in 150 nm technology. The 110 nm device lithography is denoted by the identification marking letter B. For more information on how to identify products by the Process Identification Letter, please refer to AN1995 Serial Flash Memory Device Marking or contact your nearest Numonyx Sales Office. Note: For available options speed, package, etc. or for further information on this device, please contact your nearest Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard 55/61 Ordering Information, Standard Parts M25P40 JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 56/61 M25P40 Ordering Information, Automotive Parts 13 Ordering Information, Automotive Parts Table Ordering information scheme Example: M25P40 Device Type M25P = Serial Flash memory for code storage Device Function 40 = 4 Mbit 512 Kbit x 8 Security features = no extra security Operating Voltage V = VCC = V to V Package MN = SO8N 150 mil width Device grade 6 = Industrial temperature range, to 85 °C. Device tested with High Reliability Certified flow 3 = Automotive temperature range to 125 °C Device tested with High Reliability Certified Flow. Option blank = Standard Packing T = Tape and Reel Packing Plating technology P or G = RoHS compliant Lithography /X = 150 nm technology not suggested for new design B = 110 nm , Fab 2 Diffusion Plant Automotive Grade blank = Automotive to 125 °C part A = Automotive °C to 85 °C part used ONLY in conjunction with Device Grade 6 to distinguish the Auto Tested Parts from the non Auto Tested parts . V MN 6 T P BA Note: Numonyx strongly recommends the use of the Automotive Grade devices Auto Grade 6 and 3 in an automotive envirnoment. The high reliability certified flow HRCF is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. 57/61 M25P40 Changes 12-Apr-2001 25-May-2001 11-Sep-2001 16-Jan-2002 12-Sep-2002 13-Dec-2002 12-Jun-2003 24-Nov-2003 12-Mar-2004 05-Aug-2004 03-Jan-2005 01-Aug-2005 24-Oct-2005 Document written. Serial Paged Flash Memory renamed as Serial Flash Memory. Small text changes. Notes 2 and 3 removed from Table 29 Ordering information scheme. End timing line of tSHQZ modified in Figure 25 Output timing. Updated Page Program PP instructions in Page Programming, Page Program PP , Instruction times, process technology 110 nm. 50 MHz operation added see Table 20 AC characteristics 50 MHz operation, device grade 6, VCC min = V . All packages are RoHS compliant. Blank option removed from under Plating technology in Table 29 Ordering information scheme. MLP package renamed as VFQFPN, silhouette and package mechanical drawing updated see on page 1 and Figure 29 VFDFPN8 MLP8 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 x 5 mm, package outline. 58/61 M25P40 Changes 22-Dec-2005 14-Apr-2006 05-Jun-2006 18-Dec-2006 25-Jan-2007 15-May-2007 26-Jun-2007 10-Dec-2007 15-Oct-2008 Note 2 added below Figure 26 and note 3 added below Figure 29 tRES1 and tRES2 modified in Table 20 AC characteristics 50 MHz operation, device grade 6, VCC min = V . Read Identification RDID added. Titles of Figure 29 and Table 26 corrected. The data contained in Table 12 and Table 19 is no longer preliminary data. Figure 3 Bus Master and memory devices on the SPI bus modified and Note 2 added. 40 MHz frequency condition modified for ICC3 in Table 15 DC characteristics device grade Condition changed for the Data Retention parameter in Table 12 Data retention and endurance. VWI parameter for device grade 3 added to Table 8 Power-up timing and VWI threshold. SO8 package specifications updated see Figure 26 and Table /X process added to Table 29 Ordering information scheme. tRES1 and tRES2 parameter timings changed for devices produced with the “X” process technology in Table 19 and Table SO8 Narrow package specifications updated see Figure 26 and Table Hardware Write Protection feature added on page Small text changes. Section VCC supply voltage and Section VSS ground added. Figure 3 Bus Master and memory devices on the SPI bus modified, note 2 removed and replaced by explanatory paragraph. WIP bit behavior specified at Power-up in Section 7 Power-up and Power-down. TLEAD added to Table 9 Absolute maximum ratings and VIO max modified. VFQFPN8 package specifications updated see Table 26 and Figure VCC voltage range from W17 2007 is extended to V to V. Table 21 AC characteristics 33 MHz operation, device grade 6, VCCmin V added. AC characteristics at 40 MHz removed. 40 MHz operation added see Table 21 AC characteristics *40 MHz operation, device grade 6, VCC min = V . Removed the note below Table Removed “AC characteristics 33 MHz operation, device grade 6, VCCmin V ” Table. Modified the note below Table Changed test condition for ICC3 in Table Changed clock frequency, from 20 to 25 MHz, in Table 20 and Table Added Numonyx Branding. Changed frequency up to 75 MHz only in the standard Vcc range . Added new packages. 16 Added UID/CFD protection. Extended Vcc range to V. 59/61 M25P40 Changes 18-February2009 14-May-2009 23-Feb-2010 14-April-2010 Table 8 Vwi Min Grade 3 = 1V vs. 2.1V or remove one row & Grade indication Table 11 Erase/Program cycles = cycles also for Grade 3 instead of 10000 Table 13 Icc3 Operating Current READ ' change on section Test Condition OLD C = 0.1VCC / 0.9.VCC at 40 MHz and 75 MHz, Q = open NEW C = 0.1VCC / 0.9.VCC at 40 MHz, 50 MHz and 75 MHz, Q = open OLD C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open NEW C = 0.1VCC / 0.9.VCC at 25 MHz and 33 MHz, Q = open Table 14 Icc3 Operating Current READ ' change on section Test Condition OLD C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open NEW C = 0.1VCC / 0.9.VCC at 25 MHz and 75 MHz, Q = open OLD C = 0.1VCC / 0.9.VCC at 20 MHz, Q = open NEW C = 0.1VCC / 0.9.VCC at 20 MHz and 33 MHz, Q = open Table 15 this is valid also for grade 3: OLD Instruction times, process technology 110 nm device grade 6 NEW Instruction times, process technology 110 nm

PDF Datasheet Preview

Forté Serial Flash Memory M25P40
4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface
- 4 Mbit of Flash memory - V to V single supply voltage - SPI bus compatible serial interface - 75 MHz clock rate maximum - Page Program up to 256 bytes in ms
typical - Sector Erase 512 Kbit in s typical - Bulk Erase 4 Mbit in s typical - Deep Power-down mode 1 µA typical - Hardware Write Protection protected area
size defined by three non-volatile bits BP0, BP1 and BP2 - Electronic signatures JEDEC standard two-byte signature
2013h Unique ID code UID with 16 bytes read-
only, available upon customer request RES instruction, one-byte, signature 12h ,
for backward compatibility - Packages

RoHS compliant - Automotive grade parts available

SO8 MN 150 mils width

DFN8 MS MLP8 6 x 5 mm

UFDFPN8 MB MLP8 2 x 3 mm

SO8W MW 208 mils width

VFDFPN8 MP MLP8 6 x 5 mm

UFDFPN8 MC MLP8 4 x 3 mm

April 2010
1/61

Contents

Contents

M25P40

Description 6

Signal description 8

Serial Data output Q 8

Serial Data input D 8

Serial Clock C 8

Chip Select S 8

Hold 8

Write Protect W 8

VCC supply voltage 9 VSS ground 9

SPI modes 10

Operating features 12

Page Programming 12

Sector Erase and Bulk Erase 12

Polling during a Write, Program or Erase cycle 12

Active Power, Standby Power and Deep Power-down modes 12

Status Register 13

Protection modes 13

Hold condition 14

Memory organization 16

Instructions 18

Write Enable WREN 19
Ordering Information, Standard Parts 55
Ordering Information, Automotive Parts 57
3/61

List of tables

List of tables

M25P40

Table

Table

Table

Table

Table

Table
4/61

M25P40

List of figures

List of figures

Figure Logic diagram 6 Figure SO and MLP8 connections 7 Figure Bus Master and memory devices on the SPI bus 10 Figure SPI modes supported 11 Figure Hold condition activation 15 Figure Block diagram 17 Figure Write Enable WREN instruction sequence 19 Figure Write Disable WRDI instruction sequence 20 Figure Read Identification RDID instruction sequence and data-out sequence 22 Figure Read Status Register RDSR instruction sequence and data-out sequence 23 Figure Write Status Register WRSR instruction sequence 24 Figure Read Data Bytes READ instruction sequence and data-out sequence 26 Figure Read Data Bytes at Higher Speed FAST_READ instruction sequence
and data-out sequence 28 Figure Page Program PP instruction sequence 29 Figure Sector Erase SE instruction sequence 30 Figure Bulk Erase BE instruction sequence 31 Figure Deep Power-down DP instruction sequence 32 Figure Release from Deep Power-down and Read Electronic Signature RES instruction
sequence and data-out sequence 34 Figure Release from Deep Power-down instruction sequence 34 Figure Power-up timing 36 Figure AC measurement I/O waveform 41 Figure Serial input timing 46 Figure Write Protect setup and hold timing during WRSR when SRWD = 1 46 Figure Hold timing 47 Figure Output timing 47 Figure SO8 narrow 8 lead plastic Small Outline, 150 mils body width, package outline. 48 Figure SO8W 8 lead plastic small outline, 208 mils body width, package outline. 49 Figure DFN8 MLP8 8-lead, dual flat package no lead, 6 x 5 mm, package outline 50 Figure VFDFPN8 MLP8 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 x 5 mm, package outline 51 Figure UFDFPN8 MLP8 8-lead ultra thin fine pitch dual flat package no lead, 4 x 3 mm package mechanical data52 Figure UFDFPN8 MLP8 8-lead ultra thin fine pitch dual flat package no lead, 2 x 3 mm package outline54
5/61

M25P40

The M25P40 is a 4 Mbit 512 K x 8 Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The M25P40 features high performance instructions allowing clock frequency up to 75 MHz. 1

The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.

The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes.

The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

In order to meet environmental requirements, Numonyx offers the M25P40 in RoHS compliant packages, which are Lead-free. RoHS specifications are available at:

Important:

This datasheet details the functionality of the M25P40 devices, based on the previous 150 nm process or based on the current 110 nm process available since August The new device in the 110 nm process has the following additional features and is completely backward compatible with the old one in 150 nm:
- improved max frequency Fast Read to 75 MHz in the standard Vcc range V to V, while the max frequency Fast Read in the extended Vcc range V to V is 40 MHz
- UID/CFD protection feature

Figure Logic diagram VCC

D C S W HOLD

Q M25P40

AI04090
6/61
75 MHz operation is available only on the VCC range V - V and for 110 nm process technology devices, identified by process identification digit "4" in the device marking and process letter "B" in the part number.

M25P40

Table Signal names Signal name

Function

C D Q S W HOLD VCC VSS

Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground

Figure SO and MLP8 connections

Direction Input Output Input

M25P40

S1 Q2
8 VCC 7 HOLD

VSS 4

AI04091B

There is an exposed central pad on the underside of the MLP8 packages. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

See Section 11 Package mechanical for package dimensions, and how to identify pin-1.
7/61
Details of how to find the technology process in the marking are given in AN1995, see also Section 12 Ordering Information, Standard Parts.
75 MHz operation is available only on the VCC range V - V the maximum frequency in the extended Vcc range V to V is 40 MHz.

Typical values given for TA = 25 °C. tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production.

Expressed as a slew-rate.

Only applicable as a constraint for a WRSR instruction when SRWD is set at

Figure Serial input timing
tSHSL

S tCHSL
tSLCH
tCHSH
tSHCH

C tDVCH
tCHCL
tCHDX
tCLCH

MSB IN

LSB IN

High Impedance Q

Figure Write Protect setup and hold timing during WRSR when SRWD = 1

W tWHSL
tSHWL

High Impedance Q

AI07439
46/61

M25P40 Figure Hold timing
tCHHL tHLQZ

HOLD

Figure Output timing

C tCLQV
tCLQX Q
tCLQX
tCLQV

ADDR.

D LSB IN

DC and AC parameters
tHLCH tCHHH
tHHCH tHHQX

AI02032
tSHQZ
tQLQH tQHQL

LSB OUT
Ordering Information, Standard Parts
12 Ordering Information, Standard Parts
Table Ordering information scheme

Example:M25P40

V MN 6 T

Device Type

M25P = Serial Flash memory for code storage

Device Function
40 = 4 Mbit 512 K x 8 Security features 1
= no extra security

S = CFD programmed with UID

Operating Voltage

V = VCC = V to V Package 2

MN = SO8N 150 mil width

MP = VFDFPN8 6 x 5 mm MLP8

MW = SO8W 208 mils width MS = DFN8 MLP8 2 , 6 x 5 mm

MB = UFDFPN8 MLP8 , 2 x 3 mm

MC = UFDFPN8 MLP8 , 4 x 3 mm

Device grade
6 = Industrial temperature range, to 85 °C. Device tested with standard test flow. 3 = Automotive temperature range to 125 °C . Device tested with High Reliability Certified Flow. 4

Option
blank = Standard Packing

T = Tape and Reel Packing

Plating technology

P or G = RoHS compliant Lithography 5
/X = 150 nm technology
/4 = 110 nm, Catania Diffusion Plant

B = 110 nm , Fab 2 Diffusion Plant

Automotive Grade A 4 = Automotive part to 125 °C . Device tested with High Reliability Certified Flow 3

Secure options are available upon customer request.

Exposed pad of 3 x 3 mm.

Device grade 3 available in an SO8 RoHS compliant package.

Numonyx strongly recommends the use of the Automotive Grade devices Autograde 6 and grade 3 for use in an automotive environment. The High Reliability Certified Flow HRCF is described in the quality note QNEE9801. Please ask your nearest Numonyx sales office for a copy.

The letter /X denotes the automotive grade 3 device in 150 nm technology. The 110 nm device lithography is denoted by the identification marking letter B. For more information on how to identify products by the Process Identification Letter, please refer to AN1995 Serial Flash Memory Device Marking or contact your nearest Numonyx Sales Office.

Note:

For available options speed, package, etc. or for further information on this device, please contact your nearest Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard
55/61
Ordering Information, Standard Parts

M25P40

JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
56/61

M25P40
Ordering Information, Automotive Parts
13 Ordering Information, Automotive Parts
Table Ordering information scheme

Example:

M25P40

Device Type

M25P = Serial Flash memory for code storage

Device Function
40 = 4 Mbit 512 Kbit x 8

Security features
= no extra security

Operating Voltage

V = VCC = V to V Package

MN = SO8N 150 mil width

Device grade
6 = Industrial temperature range, to 85 °C. Device tested with High Reliability Certified flow
3 = Automotive temperature range to 125 °C

Device tested with High Reliability Certified Flow.

Option
blank = Standard Packing

T = Tape and Reel Packing

Plating technology

P or G = RoHS compliant

Lithography
/X = 150 nm technology not suggested for new design

B = 110 nm , Fab 2 Diffusion Plant

Automotive Grade
blank = Automotive to 125 °C part

A = Automotive °C to 85 °C part used ONLY in
conjunction with Device Grade 6 to distinguish the Auto

Tested Parts from the non Auto Tested parts .

V MN 6 T P BA

Note:

Numonyx strongly recommends the use of the Automotive Grade devices Auto Grade 6 and 3 in an automotive envirnoment. The high reliability certified flow HRCF is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy.
57/61

M25P40

Changes
12-Apr-2001 25-May-2001
11-Sep-2001
16-Jan-2002 12-Sep-2002 13-Dec-2002 12-Jun-2003 24-Nov-2003 12-Mar-2004 05-Aug-2004 03-Jan-2005 01-Aug-2005
24-Oct-2005

Document written.

Serial Paged Flash Memory renamed as Serial Flash Memory.
Small text changes. Notes 2 and 3 removed from Table 29 Ordering information
scheme.

End timing line of tSHQZ modified in Figure 25 Output timing.

Updated Page Program PP instructions in Page Programming, Page Program PP , Instruction times, process technology 110 nm.
50 MHz operation added see Table 20 AC characteristics 50 MHz operation,
device grade 6, VCC min = V . All packages are RoHS compliant. Blank option
removed from under Plating technology in Table 29 Ordering information scheme. MLP package renamed as VFQFPN, silhouette and package mechanical drawing
updated see on page 1 and Figure 29 VFDFPN8 MLP8 8-lead Very thin Fine
pitch Quad Flat Package No lead, 6 x 5 mm, package outline.
58/61

M25P40

Changes
22-Dec-2005
14-Apr-2006
05-Jun-2006 18-Dec-2006 25-Jan-2007 15-May-2007 26-Jun-2007 10-Dec-2007 15-Oct-2008

Note 2 added below Figure 26 and note 3 added below Figure 29
tRES1 and tRES2 modified in Table 20 AC characteristics 50 MHz operation, device grade 6, VCC min = V .

Read Identification RDID added. Titles of Figure 29 and Table 26 corrected.

The data contained in Table 12 and Table 19 is no longer preliminary data.

Figure 3 Bus Master and memory devices on the SPI bus modified and Note 2
added.
40 MHz frequency condition modified for ICC3 in Table 15 DC characteristics
device grade

Condition changed for the Data Retention parameter in Table 12 Data retention and
endurance. VWI parameter for device grade 3 added to Table 8 Power-up timing and VWI threshold.

SO8 package specifications updated see Figure 26 and Table
/X process added to Table 29 Ordering information scheme.
tRES1 and tRES2 parameter timings changed for devices produced with the “X”
process technology in Table 19 and Table

SO8 Narrow package specifications updated see Figure 26 and Table

Hardware Write Protection feature added on page Small text changes. Section VCC supply voltage and Section VSS ground added.

Figure 3 Bus Master and memory devices on the SPI bus modified, note 2 removed
and replaced by explanatory paragraph.

WIP bit behavior specified at Power-up in Section 7 Power-up and Power-down. TLEAD added to Table 9 Absolute maximum ratings and VIO max modified. VFQFPN8 package specifications updated see Table 26 and Figure

VCC voltage range from W17 2007 is extended to V to V.

Table 21 AC characteristics 33 MHz operation, device grade 6, VCCmin V added.

AC characteristics at 40 MHz removed.
40 MHz operation added see Table 21 AC characteristics *40 MHz operation,
device grade 6, VCC min = V .

Removed the note below Table

Removed “AC characteristics 33 MHz operation, device grade 6, VCCmin V ”

Table.

Modified the note below Table

Changed test condition for ICC3 in Table

Changed clock frequency, from 20 to 25 MHz, in Table 20 and Table

Added Numonyx Branding.

Changed frequency up to 75 MHz only in the standard Vcc range . Added new packages. 16 Added UID/CFD protection. Extended Vcc range to V.
59/61

M25P40

Changes
18-February2009
14-May-2009 23-Feb-2010 14-April-2010

Table 8 Vwi Min Grade 3 = 1V vs. 2.1V or remove one row & Grade indication

Table 11 Erase/Program cycles = cycles also for Grade 3 instead of 10000

Table 13 Icc3 Operating Current READ ' change on section Test Condition

OLD C = 0.1VCC / 0.9.VCC at 40 MHz and 75 MHz, Q = open

NEW C = 0.1VCC / 0.9.VCC at 40 MHz, 50 MHz and 75 MHz, Q = open

OLD C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open

NEW C = 0.1VCC / 0.9.VCC at 25 MHz and 33 MHz, Q = open

Table 14 Icc3 Operating Current READ ' change on section Test Condition

OLD C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open

NEW C = 0.1VCC / 0.9.VCC at 25 MHz and 75 MHz, Q = open

OLD C = 0.1VCC / 0.9.VCC at 20 MHz, Q = open

NEW C = 0.1VCC / 0.9.VCC at 20 MHz and 33 MHz, Q = open

Table 15 this is valid also for grade 3:

OLD Instruction times, process technology 110 nm device grade 6

NEW Instruction times, process technology 110 nm

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M25P40-VMP6G Datasheet file may be downloaded here without warranties.

Datasheet ID: M25P40-VMP6G 648283