88P8341BHGI

88P8341BHGI Datasheet

IDT88P8341

Part	Datasheet
88P8341BHGI	88P8341BHGI (pdf)

PDF Datasheet Preview
SPI EXCHANGE SPI-3 TO SPI-4 Issue IDT88P8341 • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping SPI-3 <-> SPI-4 tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors - Fragment and burst length configurable per interface min 16 bytes, max 256 bytes • Standard Interfaces - OIF SPI-3 8 or 32 bit, MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2 80 - 400 MHz, 256 address range, 64 concurrently active LPs - SPI-4 FIFO status channel options • LVDS full-rate • LVTTL eighth-rate - Compatible with Network Processor Streaming Interface NPSI NPE-Framer mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - SPI-4 egress LVDS programmable lane pre-skew to cycle - IEEE JTAG - Serial or parallel microprocessor interface for control and monitoring • Full Suite of Performance Monitoring Counters - Number of packets - Number of fragments - Number of errors - Number of bytes • Green parts available, see ordering information • Ethernet transport • SONET / SDH packet transport line cards • Broadband aggregation • Multi-service switches • IP services equipment The IDT88P8341 is a SPI System Packet Interface Exchange with a SPI3 interface and a SPI-4 interface. The data that enter on the low speed interface SPI-3 are mapped to logical identifiers LIDs and enqueued for transmission over the high speed interface SPI-4 . The data that enter on the high speed interface SPI-4 are mapped to logical identifiers LIDs and enqueued for transmission over the low speed interface SPI-3 . A data flow between SPI3 and SPI-4 interfaces is accomplished with LID maps. The logical port addresses and number of entries in the LID maps may be dynamically configured. Various parameters of a data flow may be configured by the user such as buffer memory size and watermarks. In a typical application, the IDT88P8341 enables connection of a SPI-3 device to a SPI-4 network processor. In other applications a SPI-4 device may be connected to a SPI-3 network processor or traffic manager. FUNCTIONAL BLOCK DIAGRAM SPI-3 64 Logical Ports SPI-3 to SPI-4 PFP SPI-4 to SPI-3 PFP SPI-4 64 Logical Ports JTAG IF Control Path Uproc IF Clock Generator Data Path PFP = Packet Fragment Processor 6372 drw01 IDT and the IDT logo are trademarks of Integrated Device Technology, Inc INDUSTRIAL TEMPERATURE RANGE Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. APRIL 2006 DSC-6372/9 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE Table of Contents Features 1 Applications 1 Introduction 8 Pin description 9 External interfaces 13 SPI-3 13 SPI-3 ingress 13 SPI-3 egress 15 SPI-4 17 SPI-4 ingress 17 SPI-4 egress 20 SPI-4 startup handshake 20 Microprocessor interface 22 Datapath and flow control 23 SPI-3 to SPI-4 datapath and flow control 25 SPI-4 to SPI-3 datapath and flow control 30 Microprocessor interface to SPI-3 datapath 33 SPI-3 to ingress microprocessor interface datapath 33 Microprocessor insert to SPI-3 egress datapath 34 Microprocessor interface to SPI-4 egress datapath 35 SPI-4 ingress to microprocessor interface datapath 36 Performance monitor and diagnostics 37 Mode of operation 37 Counters 37 LID associated event counters 37 Non - LID associated event counters 37 Captured events 37 Non LID associated events 37 LID associated events 37 Non critical events 37 Critical events 37 Timebase 37 Internally generated timebase 37 Externally generated timebase 37 Clock generator 38 Loopbacks 39 SPI-3 Loopback 39 Operation guide 40 Hardware operation 40 System reset 40 Power on sequence 40 Clock domains 40 Software operation 40 Chip configuration sequence 40 Logical Port activation and deactivation 41 Buffer segment modification 41 Manual SPI-4 ingress LVDS bit alignment 41 SPI-4 status channel software 42 IDT88P8341 layout guidelines 42 Software Eye-Opening Check on SPI-4 Interface 43 Register description 45 Register access summary 45 Direct register format 45 Indirect register format 45 Direct access registers 49 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE Table of Contents Continued Indirect registers for SPI-3A module 54 Block base 0x0000 registers 55 Block base 0x0200 registers 55 Block base 0x0500 registers 56 Block base 0x0700 registers 57 Block base 0x0A00 registers 59 Block base 0x0C00 registers 59 Block base 0x0100 registers 62 Block base 0x1100 registers 62 Block base 0x1200 registers 62 Block base 0x1300 registers 63 Block base 0x1600 registers 64 Block base 0x1700 registers 64 Block base 0x1800 registers 64 Block base 0x1900 registers 65 Common module indirect registers Module_base 0x8000 66 Common module block base 0x0000 registers 67 Common module block base 0x0100 registers 67 Common module block base 0x0200 registers 67 Common module block base 0x0300 registers 67 Common module block base 0x0400 registers 70 Common module block base 0x0500 registers 70 Common module block base 0x0600 registers 71 Common module block base 0x0700 registers 71 Common module block base 0x0800 registers 73 JTAG interface 77 Electrical and Thermal Specifications 77 11.1Absolute maximum ratings 77 Recommended Operating Conditions 77 Terminal Capacitance 78 Thermal Characteristics 78 DC Electrical characteristics 79 11.6AC characteristics 80 SPI-3 I/O timing 80 SPI-4 LVDS Input / Output 81 SPI-4 LVTTL Status AC characteristics 82 REF_CLK clock input 82 MCLK internal clock and OCLK[3:0] clock outputs 82 Microprocessor interface 82 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE List of Figures Figure Typical application optical port and NPU/Traffic Manager 8 Figure Data Path Diagram 8 Figure Link mode SPI-3 ingress interface 14 Figure PHY mode SPI-3 ingress interface 14 Figure Link mode SPI-3 egress interface 16 Figure PHY mode SPI-3 egress interface 16 Figure Data sampling diagram 18 Figure SPI-4 ingress state diagram 19 Figure SPI-4 egress status state diagram 21 Figure Interrupt scheme 22 Figure Definition of data flows 23 Figure Logical view of datapath configuration using PFPs 24 Figure SPI-3 ingress to SPI-4 egress packet fragment processor 25 Figure SPI-3 ingress LP to LID map 27 Figure SPI-4 egress LID to LP map 28 Figure SPI-3 ingress to SPI-4 egress datapath 28 Figure SPI-3 ingress to SPI-4 egress flow control path 29 Figure SPI-4 ingress to SPI-3 egress packet fragment processor 30 Figure SPI-4 ingress to SPI-3 egress datapath 31 Figure SPI-4 ingress to SPI-3 egress flow control 32 Figure 21 Microprocessor data capture buffer 33 Figure SPI-3 ingress to microprocessor capture interface datapath 33 Figure Microprocessor interface to SPI-3 egress detailed datapath diagram 34 Figure Microprocessor data insert buffer 34 Figure Microprocessor data insert buffer 35 Figure Microprocessor data insert interface to SPI-4 egress datapath 35 Figure Microprocessor data capture buffer 36 Figure SPI-4 ingress to microprocessor data capture interface path 36 Figure Clock generator 38 Figure SPI-3 Loopback diagram 39 Figure Power-on-Reset Sequence 40 Figure DDR interface and eye opening check through over sampling 43 Figure Direct & indirect access 45 Figure SPI-3 I/O timing diagram 80 Figure SPI-4 I/O timing diagram 81 Figure Microprocessor parallel port Motorola read timing diagram 83 Figure Microprocessor parallel port Motorola write timing diagram 84 Figure Microprocessor parallel port Intel mode read timing diagram 85 Figure Microprocessor parallel port Intel mode write timing diagram 86 Figure Microprocessor serial peripheral interface timing diagram 87 Figure IDT88P8341 820PBGA package, bottom view 92 Figure IDT88P8341 820PBGA package, top and side views 93 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE List of Tables Table 1 I/O types 9 Table 2 SPI-3 ingress interface pin definition 9 Table 3 SPI-3 egress interface pin definition 10 Table 4 SPI-3 status interface pin definition 10 Table 5 SPI-4 ingress interface definition 11 Table 6 SPI-4 egress interface definition 11 Table 7 Parallel microprocessor interface 12 Table 8 Serial microprocessor interface serial peripheral interface mode 12 Table 9 Miscellaneous 12 Table 10 Both attached devices start from reset status 20 Table 11 Ingress out of synch, egress in synch 20 Table 12 Ingress in synch, egress out of synch 20 Table 13 - DIRECTION code assignment 26 Table 14 CK_SEL[3:0] input pin encoding 38 Table 15 - Zero margin SPI-3 timing budget 42 Table 16 - Margin check for SPI-3 timing 42 Table 17 - Bit order within an 8-Bit data register 45 Table 18 - Bit order within a 32-Bit data register 45 Table 19 - Bit order within an 8-Bit data register 45 Table 20 - Bit order within a 16-Bit address register 46 Table 21 - Bit order within an 8-Bit control register 46 Table 22 - Module base address Module_base 46 Table 23 - Indirect access block bases for Module A 46 Table 24 - Indirect access block bases for common module 47 Table 25 - Indirect access data registers direct accessed space at 0x30 to 0x33 47 Table 26 - Indirect access address register direct accessed space at 0x34 to 0x35 47 Table 27 - Indirect access control register direct accessed space at 0x3F 47 Table 28 - Error coding table 48 Table 29 - Direct mapped Module A registers 49 Table 30 - Direct mapped other registers 49 Table 31 - SPI-3 data capture control register 0x00 49 Table 32 - SPI-3 data Capture register 0x01 49 Table 33 - SPI-4 data insert control register 0x02 50 Table 34 - SPI-4 data insert register 0x03 50 Table 35 - SPI-4 data capture control registers register 0x04 50 Table 36 - SPI-3 data insert control register 0x05 50 Table 37 - SPI-4 data capture register 0x06 50 Table 38 - SPI-3 data insert register 0x07 50 Table 39 - Software reset register 0x20 in the direct accessed space 51 Table 40 - SPI-4 status register 0x22 in the direct accessed space 51 Table 41 - SPI-4 enable register 0x23 in the direct accessed space 51 Table 42 - Module status register 0x24 in the direct accessed space 52 Table 43 - Module enable register 0x28 in the direct accessed space 52 Table 44 - Primary interrupt status register 0x2C in the direct accessed space 53 Table 45 - Secondary interrupt status register 0x2D in the direct accessed space 53 Table 46 - Primary interrupt enable register 0x2E in the direct accessed space 53 Table 47 - Secondary interrupt enable register 0x2F in the direct accessed space 53 Table 48 - Module A indirect register 54 Table 49 - SPI-3 ingress LP to LID map 55 Table 50 - SPI-3 general configuration register register_offset=0x00 55 Table 51 - SPI-3 ingress configuration register register_offset=0x01 56 Table 52 - SPI-3 ingress fill level register register_offset=0x02 56 Table 53 - SPI-3 ingress max fill level register register_offset=0x03 56 Table 54 - SPI-3 egress LID to LP map 56 Table 55 - SPI-3 egress configuration register register_offset=0x00 57 Table 56 - SPI-4 ingress to SPI-3 egress flow control register register_offset=0x01 57 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE List of Tables Continued Table 57 - SPI-3 egress test register register_offset=0x02 57 Table 58 - SPI-3 egress fill level register register_offset=0x03 58 Table 59 - SPI-3 egress max fill level register register_offset=0x04 58 Table 60 - LID associated event counters 0x000-0x17F 59 Table 61 - Non LID associated event counters 0x00 - 0x0B 59 Table 62 - Non LID associated interrupt indication register register_offset 0x0c 60 Table 63 - Non LID associated interrupt enable register register_offset 0x0D 60 Table 64 - LID associated interrupt indication register register_offset 0x0E 60 Table 65 - LID associated interrupt enable register register_offset 0x0F 60 Table 66 - Non critical LID associated capture table register_offset 0x10-0x15 61 Table 67 - SPI-3 to SPI-4 critical LID interrupt indication registers register_offset 0x16-0x17 61 Table 68 - SPI-3 to SPI-4 critical LID interrupt enable registers register_offset 0x18-0x19 61 Table 69 - SPI-4 to SPI-3 critical LID interrupt indication registers register_offset 0x1A-0x1B 61 Table 70 - SPI-4 to SPI-3 critical LID interrupt enable registers register_offset 0x1C-0x1D 61 Table 71 - Critical events source indication register register_offset 0x1E 61 Table 72 - SPI-3 ingress packet length configuration register 62 Table 73 - SPI-4 egress port descriptor table 64 entries 62 Table 74 - SPI-4 egress DIRECTION code assignment 62 Table 75 - SPI-3 ingress port descriptor table Block_base 0x1200 62 Table 76 - SPI-3 to SPI-4 PFP register register_offset 0x00 63 Table 77 - NR_LID field encoding 63 Table 78 - SPI-3 to SPI-4 flow control register register_offset 0x01 63 Table 79 - SPI-4 ingress packet length configuration 64 entries configurable 64 Table 80 - SPI-3 egress port descriptor table 64 entries 64 Table 81 - SPI-3 egress DIRECTION code assignment 64 Table 82 - SPI-4 ingress port descriptor tables 64 entries 64 Table 83 - SPI-4 to SPI-3 PFP register 0x00 65 Table 84 - NR_LID field encoding 65 Table 85 -Common Module Module_base 0x8000 indirect register table 66 Table 86 - SPI-4 ingress LP to LID map 256 entries, one per LP 67 Table 87 - SPI-4 ingress calendar_0 256 entries 67 Table 88 - SPI-4 ingress calendar_1 256 entries 67 Table 89 - SPI-4 ingress configuration register 0x00 67 Table 90 - SPI-4 ingress status configuration register register_offset 0x01 68 Table 91 - SPI-4 ingress status register register_offset 0x02 68 Table 92 - SPI-4 ingress inactive transfer port register_offset 0x03 68 Table 93 - SPI-4 ingress calendar configuration register 0x04 to 0x05 69 Table 94 SPI-4 ingress watermark register register_offset 0x06 69 Table 95 - SPI-4 ingress fill level register register_offset 0x07 69 Table 96 - SPI-4 ingress max fill level register register_offset 0x0B 69 Table 97 - SPI-4 ingress diagnostics register register_offset 0x0F 69 Table 98 - SPI-4 ingress DIP-4 error counter register_offset 0x10 70 Table 99 - SPI-4 ingress bit alignment control register register_offset 0x11 70 Table 100 - SPI-4 ingress start up training threshold register register_offset 0x12 70 Table 101 - SPI-4 egress LID to LP map 256 entries 70 Table 102 - SPI-4 egress calendar_0 256 locations 70 Table 103 - SPI-4 egress calendar_1 256 locations 71 Table 104 SPI-4 egress configuration register_0 register_offset 0x00 71 Table 105 - SPI-4 egress configuration register_1 register_offset 0x01 71 Table 106 - SPI-4 egress status register register_offset 0x02 72 Table 107 - SPI-4 egress calendar configuration register Register_offset 0x03 - 0x04 72 Table 108 - SPI-4 egress diagnostics register register_offset 0x05 72 Table 109 - SPI-4 egress DIP-2 error counter register_offset 0x06 72 Table 110 - SPI-4 ingress bit alignment window register register_offset 0x00 73 Table 111 - SPI-4 ingress lane measure register register_offset 0x01 73 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE List of Tables Continued Table 112 - SPI-4 ingress bit alignment counter register 0x02 to 0x0B 73 Table 113 - SPI-4 ingress manual alignment phase/result register 0x0C to 0x1F 73 Table 114 - SPI -4 egress data lane timing register register_offset 0x2A 73 Table 115 - SPI-4 egress Control Lane Timing register Register_offset 0x2B 74 Table 116 - SPI-4 egress data clock timing register register_offset 0x2C 74 Table 117 - SPI-4 egress status timing register register_offset 0x2D 74 Table 118 - SPI-4 egress status clock timing register register_offset 0x2E 74 Table 119 - PMON timebase control register register_offset 0x00 75 Table 120 - Timebase register register_offset 0x01 75 Table 121 - Clock generator control register register_offset 0x10 75 Table 122 - OCLK and MCLK frequency select encoding 75 Table 123 - GPIO register register_offset 0x20 76 Table 124 - GPIO monitor table 5 entries 0x21-0x25 for GPIO[0] through GPIO[4] 76 Table 125 - Version number register register_offset 0x30 76 Table 126 JTAG instructions 77 Table 127 maximum ratings 77 Table 128 Recommended Operating Conditions 77 Table 129 Terminal Capacitance 78 Table 130 Thermal Characteristics 78 Table 131 DC Electrical characteristics 79 Table 132 SPI-3AC Input / Output timing specifications 80 Table 133 SPI-4.2 LVDSAC Input / Output timing specifications 82 Table 134 SPI-4 LVTTL status AC Characteristics 82 Table 135 REF_CLK clock input 82 Table 136 OCLK[3:0] clock inputs and MCLK internal clock 82 Table 137 Microprocessor interface 82 Table 138 Microprocessor parallel port Motorola read timing 83 Table 139 Microprocessor parallel port Motorola write timing 84 Table 140 Microprocessor parallel port Intel mode read timing 85 Table 141 Microprocessor parallel port Intel mode write timing 86 Table 142 Microprocessor serial peripheral interface timing 87 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Exchange between optical ports and NPU/Traffic Manager INDUSTRIAL TEMPERATURE RANGE OC-48/ 4xOC-12/ 16xOC-3 Multi-Rate SONET SPI-3 IDT88P8341 SPI-4 Framer 6372 drw02 Control Processor Figure Typical application optical port and NPU/Traffic Manager INTRODUCTION The IDT88P8341 device is a SPI-3 to SPI-4 exchange intended for use in optical line cards, Ethernet transport, and multi-service switches. The SPI3 and SPI-4 interfaces are defined by the Optical Interworking Forum. The device can be used as a rate adapter, a switch, or an aggregation device between network processor units, multi-gigabit framers and PHYs, and switch fabric interface devices. DATA PATH OVERVIEW Figure Data Path Diagram shows an overview of the data path through the device. In normal operation, there are two paths through the IDT88P8341 device the SPI-3 ingress to SPI-4 egress path, and the SPI-4 ingress to SPI-3 egress path. SPI-3 and SPI-4 burst sizes are separately configurable. In the SPI-3 ingress to SPI-4 egress path, data enter in fragments on the SPI3 interface and are received by the SPI-3 interface block. The fragments are mapped to a SPI-4 address and stored in memory allocated at the SPI-3 level until such a time that the Packet Fragment Processor determines that they are to be transmitted on the SPI-4 interface. The data is transferred in bursts, in line with the OIF SPI-4 implementation agreement, to the SPI-4 interface block, and are transmitted on the SPI-4 interface. In the SPI-4 ingress to SPI-3 egress path, data enter in bursts on the SPI-4 interface and are received by the SPI-4 interface block. The SPI-4 address is translated to a SPI-3 address, and the data contained in the bursts are stored in memory allocated at the SPI-3 level until such a time that the Packet Fragment Processor determines that they are to be transmitted on the SPI-3 interface. The data is transferred in packet fragments, in line with the OIF SPI-3 implementation agreement, to the SPI-3 interface block, and are transmitted on the SPI-3 interface. • Eight ADR signals supported for PTPA in packet-level mode - Address range 0 to 255 with support for 64 simultaneously active logical ports - Fragment length section configurable from 16 to 256 bytes in 16 byte multiples - Configurable standard and non-standard bit ordering SPI-3 implementation features The following are implemented per SPI-3 interface, and there are two instantiations per device. - Link / PHY layer device - Packet / byte level FIFO status information - Physical port enable - Width of data bus 32 bit or 8 bit - Parity selection odd or even - Enable parity check SPI-3 ingress The following are implemented per SPI-3 interface, and there are 4 instantiations per device. - SPI-3 LP to Link Identifier LID map - 256 entries, one per SPI-3 LP address - LP enable control - Only 64 of these entries are to be in the active state simultaneously Backpressure enable - Link mode only - Enables the assertion of the I_ENB when at least one active LID can not accept data - If not enabled, the I_ENB signal will never be asserted in Link mode, possibly leading to fragments being discarded. Minimum packet length - Packets shorter than the minimum length will be optionally counted in the short packet counter. - Range 0 255 in 1 byte increments SPI-3 ingress interface Multiple independent data streams can be transmitted over the physical SPI- 3 port. Each of those data streams is identified by a SPI-3 logical port LP Data from a transfer on a SPI-3 logical port and the associated descriptor fields are synchronized to the configurable internal buffer segment pool. Normal operation Refer to Glossary] for details about the SPI-3 interface. • A SPI-3 interface a physical port is enabled by the SPI-3_ENABLE flag in the SPI-3 configuration register. A disabled interface tri-states all output pins and does not respond to any input signals. • The interface is configured in PHY or Link layer mode by the LINK flag in the SPI-3 general configuration register. • at most 64 logical ports can be configured. • The SPI-3 interface supports data transport over either a 32 bit data interface or over one single 8 bit interface data[7:0] only. The selection is defined by the BUSWIDTH flag in the SPI-3 general configuration register. • The SPI-3 interface is configured in byte mode or packet mode by the PACKET flag in the SPI-3 general configuration register. • The SPI-3 interface supports over-clocking. • Parity checking over data[31:0] is enabled by the PARITY_EN flag in the Table 50, SPI-3 general configuration register register_offset=0x00 . The parity type is defined by the EVEN_PARITY flag. Parity check results over the in-band port address and the data of a transfer are forwarded towards the packet fragment processor. • SPI Exchange supports zero clock interval spacing between transfers. SPI-3 ingress interface errors Given an I_FCLK within specification, the SPI-3 will not dead lock due to any combination or sequence on the SPI-3 interface. The SPI Exchange detects for incorrect SOP / EOP sequences on a logical port. The following sequences are detected: Successive SOP- SOP sequence rather than SOP Successive EOP- EOP sequence rather than SOP Detection of an illegal sequence results in the generation of an SPI-3 illegal SOP sequence event or SPI-3 illegal EOP sequence even generated. The event is associated to the physical port. The event is directed towards the PMON & DIAG module. A clock available process detects a positive I_FCLK within a 64 MCLK clock cycle period. The result of this process is reported in the I_FCLK_AV flag in the Table 52 SPI-3 ingress fill level register Block_base 0x0200 + Register_offset 0x02 . A status change from the clock available status to the clock not available status generates a maskable SPI-3 ingress clock unavailable interrupt indication, SPI3_ICLK_UN, in Table 62-Non LID associated interrupt indication register Block_Base 0x0C00 + Register_offset 0x0C . APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE SPI-3 ingress Link mode Refer to [Glossary] for details about the SPI-3 interface. • The PHY pushes data into the device in blocks from 1 up to 256 bytes. • The SPI Exchange provides backpressure for the SPI-3 ingress physical interface by the I_ENB signal. The I_ENB is asserted when at least one active LID can not accept data. This feature is enabled by the BACKPRESSURE_EN flag in the SPI-3 ingress configuration register register_offset = 0x01 . When the flag is cleared the I_ENB signal will not be asserted, hence no backpressure can be generated. I_ERR I_Data[31:0] I_PRTY RVAL I_SOP I_EOP I_RSX I_MOD[1:0] I_ENB IDT88P8341 LINK MODE I_FCLK Figure Link mode SPI-3 ingress interface 6372 drw04 SPI-3 ingress PHY mode The SPI Exchange indicates to the Link layer it has buffer space available by proper response to either Link layer polling packet mode or direct indication on DTPA signals byte mode . The selection is made by the PACKET flag in the SPI-3 configuration register. • In packet mode the device responds to polling by Link layer device • [3:0] DTPA[3:0] STPA PTPA ADDR[7:0] byte mode packet mode LINK I_ERR I_Data[31:0] I_PRTY IDT88P8341 PHY MODE I_SOP I_EOP I_RSX I_MOD[1:0] I_ENB I_FCLK SPI-3 ingress LID associated control Each LID on the SPI-3 interface has the ability to be programmed for minimum and maximum packet length. The minimum packet length can be set from 0 to 255 bytes in one byte increments. The maximum packet length can be set from 0 to 16,383 bytes in one byte increments. Each LID can be enabled and disabled independently. [LP] = LID \| EN \| BRV LID EN BRV Figure SPI-3 ingress LP to LID map 256 LPs 6372 drw15 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE SPI-4 egress interface port associated control The SPI-4 interface has an associated LID to LP map See Table 101 - SPI4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF for the purpose of directing the packet fragments from the selected SPI-3 ingress main memory buffer segment pool to the SPI-4 egress interface. The SPI-4 LID map has 256 entries, one per LID. The SPI-4 interface has an enable bit. The burst length is associated with the SPI-4 interface. The allowed burst range is 16 to 256 bytes per burst. The last burst of a packet can be shorter than the programmed burst size. SPI-4 egress LID associated control Each of the 256 entries in the SPI-4 egress LID to LP map See Table 101 - SPI-4 egress LID to LP Map 256 entries is used to control the pulling of bursts out of the buffer segment pool and into the SPI-4 egress interface. Each LID can be enabled and disabled independently. [LID] = LP \| EN 256 LIDs LP Logical Port EN LP Enable 6372 drw16 Figure SPI-4 egress LID to LP map The diagram below shows the datapath through the device from the SPI3 ingress interface to the SPI-4 egress interface. SPI-3 8 bit / 32 bit Min 19.44MHz Max 133MHz Interface Block Interface Block JTAG uproc Chip Counters Memory LID Counters Memory Main Memory SPI-3 / LID map SPI-4.2 Min 80 MHz Max:400 MHz SPI-4 / LID map 6372 drw17 Figure SPI-3 ingress to SPI-4 egress datapath 28 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE SPI-3 ingress to SPI-4 egress flow control For control information there are two separate cases to consider The case that the SPI-3 physical interface port is configured in Link mode, and the case that the SPI-3 is configured in PHY mode. Note that since the SPI-3 physical interfaces are configured separately, the device is able to deal with the case that some of the LP fragments have been received on a Link layer device SPI-3 interface and some have been received on a PHY layer device SPI-3 interface. For a device in Link mode the Link device can only control the flow of data through the RENB signal. Two modes of operation are implemented and configurable for flow control on this interface either the data can be allowed to flow freely into the device or the RENB signal will be asserted if a condition arises that one of the LPs is unable to receive another fragment. The first of these modes is considered to have no Link layer device flow control, and the second has Link layer device flow control. For the no Link flow control mode, any data sent to an LP unable to receive another fragment will cause an LP overflow. For a device in Link mode the Link has complete knowledge of the fill level of the data buffers in each of the LPs in the PHY. This knowledge is attained either through byte level polling or packet level polling. Both in Link and PHY modes, the data is collected to buffer segments associated with an LP. The SPI-4 PFP is updated with the number of free segments available to the LP. The SPI-4 PFP determines which LP to service based on two factors whether the LP contains enough data for a burst, and the starving / hungry / satisfied state of the LP. For details on the mapping of LPs to LIDs, refer to Table 101 - SPI-4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF. Direct register format All direct register accesses are one byte. The bit ordering for the direct access registers is shown. TABLE 17 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER Direct Register Format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0 Bit 7 is the most significant data bit. Indirect register format The internal format for 32 and 8 bit registers is shown below. The registers are accessed from the external processor interface as successive bytes of indirect data. The indirect register space includes 32-bit data registers and 8bit data registers. The directly-addressed register space includes directlyaddressable 8-bit data registers, four 8-bit data registers for indirect data access, two 8-bit address registers for indirect data access, and an 8-bit control register TABLE 18 - BIT ORDER WITHIN A 32-BIT DATA REGISTER Indirect Data register 0x33 Indirect Data register 0x32 Indirect Data Indirect Data register 0x31 register 0x30 bit 25 bit 16 bit 8 bit 0 Bit 31 is the most significant data bit. TABLE 19 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER Indirect Data register 0x30 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0 Bit 7 is the most significant data bit. 6372 drw29 APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 TABLE 20 - BIT ORDER WITHIN A 16-BIT ADDRESS REGISTER Indirect High Address register 0x35 Indirect Low Address register 0x34 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0 Bit 15 is the most significant data bit. TABLE 21 - BIT ORDER WITHIN AN 8-BIT CONTROL REGISTER Indirect Control register 0x3F bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0 Bit 7 is the most significant data bit. INDUSTRIAL TEMPERATURE RANGE Module base address Module_base There are two modules defined for indirect data access. TABLE 22 - MODULE BASE ADDRESS MODULE_BASE MODULE Module_base Module A SPI3-A, PFP-A, PMON-A 0x0000 Common SPI-4, timing, PMON, clock, GPIO, and version number 0x8000 Block base There are block bases defined for SPI-3 modules and also for Common, as shown in the following tables. TABLE 23 - INDIRECT ACCESS BLOCK BASES FOR MODULE A Block_base 0x0000 0x0200 0x0500 0x0700 0x0A00 0x0C00 0x1000 0x1100 0x1200 0x1300 0x1600 0x1700 0x1800 0x1900 PACKET A SPI-3 interface can be used either in BYTE or PACKET modes. A SPI-3 interface acting as a Link layer device can poll the attached PHY device for up to 64 LPs if the attached PHY device supports the polling interface. When attached to a PHY device that only supports byte mode, the four direct status indicators can be used. When the SPI Exchange is in PHY mode, the PACKET bit is used to select either a polled or direct status response to the attached Link device. 0 = BYTE mode with direct status indication for up to 4 LPs [3:0] 1= PACKET mode with polled status for up to 64 LPs SPI3_ENABLE to the state programmed into this bit. A port should be disabled to save power if it is not used. 0=SPI-3 Physical port disabled, outputs are in tristate 1=SPI-3 Physical port enabled BUSWIDTH The SPI-3 interface can be used as either a single 8-bit or 32-bit interface, according to the needs of the attached device. The SPI-3 ingress and egress of a given SPI-3 physical port will always be of the same bus width. 0=32 bit SPI-3 interface 1=8 bit SPI-3 interface EVEN_PARITY The SPI-3 interface is provisioned to generate and to check for odd or even parity. The PARITY_EN bit must be set for this to become effective. Odd parity is standard for SPI-3 interfaces. APRIL 10, 2006 IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 INDUSTRIAL TEMPERATURE RANGE 0=Odd parity on this port 1=Even parity on this port PARITY_EN generation and checking, according to the state of the EVEN_PARITY bit. 0=Disable parity on this SPI-3 port 1=Enable parity on this SPI-3 port WATERMARK The SPI-3 interface can be set to a SPI-3 ingress port watermark value. The value of 0x10 is the highest watermark that can be set, meaning all ingress buffers will be full before backpressure will be initiated on the SPI-3 ingress interface. The WATERMARK field value of 0x08 is used to set the watermark for a half-full ingress buffer before tripping backpressure. The units of WATERMARK are one-sixteenth of the available ingress buffering per unit. Each unit is equal to 128 bytes. BACKPRESSURE_EN must be set [Register_offset 0x01] for the watermark to become effective. The watermark field is usually set to 0x10, and the FREE_SEGMENT field of Table 75, SPI3 ingress port descriptor tables Block_base 0x1200 is used for per LID backpressure. SPI-3 ingress fill level register Block_base 0x0200 + Register_offset 0x02 TABLE 52 - SPI-3 INGRESS FILL LEVEL REGISTER REGISTER_OFFSET=0x02 Field Bits Length Initial Value FILL_CUR 0x00 I_FCLK_AV There is one register for SPI-3 ingress fill level register for the SPI-3 interface. The register has read-only access. The bit fields of the SPI-3 ingress fill level register are described. FILL_CUR register, the value read from it will change rapidly and is used for internal diagnostics only. I_FCLK_AV Current SPI-3 ingress clock availability is checked here. 0=SPI-3 ingress clock not detected on a SPI-3 port 1=SPI-3 ingress clock transitions detected on a SPI-3 port SPI-3 ingress configuration register Block_base 0x0200 + Register_offset 0x01 TABLE 51 - SPI-3 INGRESS CONFIGURATION REGISTER REGISTER_OFFSET=0x01 Field Bits Length Initial Value BACKPRESSURE_EN FIX_LP Reserved 31:2 0x0000 There is one SPI-3 ingress configuration register for the SPI-3 interface. The register has read and write access. The bit fields for the SPI-3 ingress configuration register are described in the following paragraphs. BACKPRESSURE_EN the SPI-3 interface can have backpressure enabled or disabled. Disabling backpressure means that data coming into the ingress may be lost if the SPI-3 interface ingress buffers overflow. The SPI-3 interface can run at full-rate, however, since there will be no backpressure. Attached devices that do not respond properly to backpressure should be interfaced by disabling backpressure. Enabling backpressure will cause the I_ENB signal to be asserted when the ingress buffer fill level is equal to the WATERMARK value [Register_offset 0x00], or the free segment buffer threshold Table 75, SPI-3 ingress port descriptor table Block_base 0x1200 has been reached for any active LID. Block base 0x0700 registers The SPI-4 ingress to SPI-3 egress flow control register has read and write access. The bit fields of the SPI-4 ingress to SPI-3 egress flow control register are described. CREDIT_EN Theflowcontrolinformationreceivedfrom the attached SPI-3 device is interpreted as status or credit information as selected by the CREDIT_EN bit in the SPI-4 ingress to SPI-3 egress flow control Register. If the status mode is used, data will be egressed until the status is changed by the attached SPI-3 device. If the credit mode is used, the SPI-3 egress will transmit only one packet fragment and then wait for an update in the internal buffer segment pool status before sending another packet fragment. 0=Status mode 1=Credit mode SPI-3 egress configuration register Block_base 0x0700 + Register_offset 0x00 TABLE 55 - SPI-3 EGRESS CONFIGURATION REGISTER REGISTER_OFFSET=0x00 Field Bits Length Initial Value POLL_LENGTH 0x0F Reserved 0b00 STX_SPACING EOP_SPACING Reserved 31:10 0x00 There is one SPI-3 egress configuration register per SPI-3 interface. The SPI-3 egress configuration registers have read and write access. A SPI-3 egress configuration registers is used to control the poll sequence length of a SPI-3 egress interface when the SPI-3 interface is in Link mode. The SPI-3 egress configuration register is used to add two cycles to STX or EOP as required to interface to the attached device. POLL_LENGTH Link layer poll sequence length when in Link mode. The poll sequence is from the LP associated with LID0 to the LP associated with the LID for POLL_LENGTH - STX_SPACING This bit is used to enable or disable the adding of two dummy STX cycles to the SPI-3 egress interface to meet the needs of an attached device. 0= No dummy STX cycles are added to the SPI-3 egress. 1= Two dummy STX cycles are added to the SPI-3 egress EOP_SPACING This bit is used to enable or disable the adding of two dummy EOP cycles to the SPI-3 egress interface to meet the needs of an attached device. 0= No dummy EOP cycles are added to the SPI-3 egress. 1= Two dummy EOP cycles are added to the SPI-3 egress SPI-4 ingress to SPI-3 egress flow control register Block_base 0x0700 + Register_offset 0x01 TABLE 56 - SPI-4 INGRESS TO SPI-3 EGRESS FLOW CONTROL REGISTER REGISTER_OFFSET=0x01 Field CREDIT_EN BURST_EN LOOP_BACK Reserved Bits Length Initial Value 31:3 0x00 BURST_EN to an LP. When this feature is not enabled, only one burst per LP is allowed into the SPI-3 egress buffers. 0=Disable burst enable 1=Enable burst enable LOOP_BACK In this mode the contents of a SPI-3 ingress are directly transferred to a SPI-3 egress buffers of the same port. This mode is useful for off-line diagnostics. 0=Disable loopback 1=Enable loopback SPI-3 egress test register Block_base 0x0700 + Register_offset 0x02 05/09/05 • Added sections System Reset and Power on Sequence p.40 . • Updated PFR to PFP in Table 49 "Module A indirect register" p.53 • Updated Table 80 "SPI-4 ingress packet length configuration" p.63 • Updated length for Reserved in Table 83 "SPI-4 ingress port descriptor" p.63 • Updated Table 87 "SPI-4 ingress LP to LID map" p.66 • Added Green to Ordering information p.94 08/05/05 • Updated Table 128 "Absolute maximum ratings" p.76 10/20/05 • Updated Table 7 "Parallel microprocessor interface" p.12 • Updated Table 131 "Thermal Characteristics" p.77 • Updated Microprocessor parallel port section p.82-85 11/09/05 • Updated Table 126 "Version number register register_offset 0x30 " p.75 12/01/05 • Updated SPI-4 status channel software p.42 01/05/06 • Updated Figure 4 "PHY mode SPI-3 ingress interface" p.14 • Deleted Table 13 "NR_LID Field Encoding". Updated SPI-4 egress queues, Normal operation section p.26 • Updated Section "SPI-4 status channel software" p.42 • Updated Table 26 title "Indirect access address register at 0x34 to 0x35" p.46 • Updated section title "Indirect registers for SPI-3A module" p.53 • Updated Table 127 "Absolute maximum ratings" p.76 • Updated Table 129 "Terminal Capacitance" p.77 04/10/06 • Initial Release of Final Datasheet with new section "Software Eye-Opening Check on SPI-4" & new Figure "DDR interface and eye opening check through over sampling" p.43-44 • Updated Clock generator pg. 38 • Updated SPI-4 ingress watermark register pg. 69 • Updated Clock generator control register pg. 75 • Updated Table 130 Thermal Characteristics pg. 78 • Updated Table 132 SPI-3 AC Input/Output timing specifications pg. 80 • Updated Table 136 OCLK[3:0] outputs and MCLK internal clock pg. 82 APRIL 10, 2006 ORDERING INFORMATION Device Type Package Process / Temperature Range Industrial -40C to +85C Green Plastic Ball Grid Array PBGA, BH820-1 NOTE Green parts are available. 88P8341 SPI Exchange SPI-3 to SPI-4 6372 drw38 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1716 email:

PDF Datasheet Preview

SPI EXCHANGE SPI-3 TO SPI-4 Issue

IDT88P8341
• Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping SPI-3 <-> SPI-4 tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors - Fragment and burst length configurable per interface min 16 bytes,
max 256 bytes
• Standard Interfaces
- OIF SPI-3 8 or 32 bit, MHz, 256 address range, 64 concurrently active LPs per interface
- One OIF SPI-4 phase 2 80 - 400 MHz, 256 address range, 64 concurrently active LPs
- SPI-4 FIFO status channel options
• LVDS full-rate
• LVTTL eighth-rate
- Compatible with Network Processor Streaming Interface NPSI NPE-Framer mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - SPI-4 egress LVDS programmable lane pre-skew to cycle - IEEE JTAG - Serial or parallel microprocessor interface for control and monitoring
• Full Suite of Performance Monitoring Counters
- Number of packets - Number of fragments
- Number of errors - Number of bytes
• Green parts available, see ordering information
• Ethernet transport
• SONET / SDH packet transport line cards
• Broadband aggregation
• Multi-service switches
• IP services equipment

The IDT88P8341 is a SPI System Packet Interface Exchange with a SPI3 interface and a SPI-4 interface. The data that enter on the low speed interface SPI-3 are mapped to logical identifiers LIDs and enqueued for transmission over the high speed interface SPI-4 . The data that enter on the high speed interface SPI-4 are mapped to logical identifiers LIDs and enqueued for transmission over the low speed interface SPI-3 . A data flow between SPI3 and SPI-4 interfaces is accomplished with LID maps. The logical port addresses and number of entries in the LID maps may be dynamically configured. Various parameters of a data flow may be configured by the user such as buffer memory size and watermarks. In a typical application, the IDT88P8341 enables connection of a SPI-3 device to a SPI-4 network processor. In other applications a SPI-4 device may be connected to a SPI-3 network processor or traffic manager.

FUNCTIONAL BLOCK DIAGRAM

SPI-3 64 Logical Ports

SPI-3 to SPI-4 PFP SPI-4 to SPI-3 PFP

SPI-4 64 Logical

Ports

JTAG IF Control Path

Uproc IF

Clock Generator

Data Path PFP = Packet Fragment Processor
6372 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

INDUSTRIAL TEMPERATURE RANGE

Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

APRIL 2006

DSC-6372/9

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

Table of Contents

Features 1 Applications 1 Introduction 8 Pin description 9 External interfaces 13

SPI-3 13 SPI-3 ingress 13 SPI-3 egress 15

SPI-4 17 SPI-4 ingress 17 SPI-4 egress 20 SPI-4 startup handshake 20

Microprocessor interface 22 Datapath and flow control 23

SPI-3 to SPI-4 datapath and flow control 25 SPI-4 to SPI-3 datapath and flow control 30 Microprocessor interface to SPI-3 datapath 33

SPI-3 to ingress microprocessor interface datapath 33 Microprocessor insert to SPI-3 egress datapath 34 Microprocessor interface to SPI-4 egress datapath 35 SPI-4 ingress to microprocessor interface datapath 36 Performance monitor and diagnostics 37 Mode of operation 37 Counters 37 LID associated event counters 37 Non - LID associated event counters 37 Captured events 37 Non LID associated events 37 LID associated events 37

Non critical events 37 Critical events 37 Timebase 37 Internally generated timebase 37 Externally generated timebase 37 Clock generator 38 Loopbacks 39 SPI-3 Loopback 39 Operation guide 40 Hardware operation 40 System reset 40 Power on sequence 40 Clock domains 40 Software operation 40 Chip configuration sequence 40 Logical Port activation and deactivation 41 Buffer segment modification 41 Manual SPI-4 ingress LVDS bit alignment 41 SPI-4 status channel software 42 IDT88P8341 layout guidelines 42 Software Eye-Opening Check on SPI-4 Interface 43 Register description 45 Register access summary 45 Direct register format 45 Indirect register format 45 Direct access registers 49

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

Table of Contents Continued

Indirect registers for SPI-3A module 54 Block base 0x0000 registers 55 Block base 0x0200 registers 55 Block base 0x0500 registers 56 Block base 0x0700 registers 57 Block base 0x0A00 registers 59 Block base 0x0C00 registers 59 Block base 0x0100 registers 62 Block base 0x1100 registers 62 Block base 0x1200 registers 62 Block base 0x1300 registers 63 Block base 0x1600 registers 64 Block base 0x1700 registers 64 Block base 0x1800 registers 64 Block base 0x1900 registers 65

Common module indirect registers Module_base 0x8000 66 Common module block base 0x0000 registers 67 Common module block base 0x0100 registers 67 Common module block base 0x0200 registers 67 Common module block base 0x0300 registers 67 Common module block base 0x0400 registers 70 Common module block base 0x0500 registers 70 Common module block base 0x0600 registers 71 Common module block base 0x0700 registers 71 Common module block base 0x0800 registers 73

JTAG interface 77 Electrical and Thermal Specifications 77
11.1Absolute maximum ratings 77 Recommended Operating Conditions 77 Terminal Capacitance 78 Thermal Characteristics 78 DC Electrical characteristics 79 11.6AC characteristics 80

SPI-3 I/O timing 80 SPI-4 LVDS Input / Output 81 SPI-4 LVTTL Status AC characteristics 82 REF_CLK clock input 82 MCLK internal clock and OCLK[3:0] clock outputs 82 Microprocessor interface 82
APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

List of Figures

Figure Typical application optical port and NPU/Traffic Manager 8 Figure Data Path Diagram 8 Figure Link mode SPI-3 ingress interface 14 Figure PHY mode SPI-3 ingress interface 14 Figure Link mode SPI-3 egress interface 16 Figure PHY mode SPI-3 egress interface 16 Figure Data sampling diagram 18 Figure SPI-4 ingress state diagram 19 Figure SPI-4 egress status state diagram 21 Figure Interrupt scheme 22 Figure Definition of data flows 23 Figure Logical view of datapath configuration using PFPs 24 Figure SPI-3 ingress to SPI-4 egress packet fragment processor 25 Figure SPI-3 ingress LP to LID map 27 Figure SPI-4 egress LID to LP map 28 Figure SPI-3 ingress to SPI-4 egress datapath 28 Figure SPI-3 ingress to SPI-4 egress flow control path 29 Figure SPI-4 ingress to SPI-3 egress packet fragment processor 30 Figure SPI-4 ingress to SPI-3 egress datapath 31 Figure SPI-4 ingress to SPI-3 egress flow control 32 Figure 21 Microprocessor data capture buffer 33 Figure SPI-3 ingress to microprocessor capture interface datapath 33 Figure Microprocessor interface to SPI-3 egress detailed datapath diagram 34 Figure Microprocessor data insert buffer 34 Figure Microprocessor data insert buffer 35 Figure Microprocessor data insert interface to SPI-4 egress datapath 35 Figure Microprocessor data capture buffer 36 Figure SPI-4 ingress to microprocessor data capture interface path 36 Figure Clock generator 38 Figure SPI-3 Loopback diagram 39 Figure Power-on-Reset Sequence 40 Figure DDR interface and eye opening check through over sampling 43 Figure Direct & indirect access 45 Figure SPI-3 I/O timing diagram 80 Figure SPI-4 I/O timing diagram 81 Figure Microprocessor parallel port Motorola read timing diagram 83 Figure Microprocessor parallel port Motorola write timing diagram 84 Figure Microprocessor parallel port Intel mode read timing diagram 85 Figure Microprocessor parallel port Intel mode write timing diagram 86 Figure Microprocessor serial peripheral interface timing diagram 87 Figure IDT88P8341 820PBGA package, bottom view 92 Figure IDT88P8341 820PBGA package, top and side views 93

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

List of Tables

Table 1 I/O types 9 Table 2 SPI-3 ingress interface pin definition 9 Table 3 SPI-3 egress interface pin definition 10 Table 4 SPI-3 status interface pin definition 10 Table 5 SPI-4 ingress interface definition 11 Table 6 SPI-4 egress interface definition 11 Table 7 Parallel microprocessor interface 12 Table 8 Serial microprocessor interface serial peripheral interface mode 12 Table 9 Miscellaneous 12 Table 10 Both attached devices start from reset status 20 Table 11 Ingress out of synch, egress in synch 20 Table 12 Ingress in synch, egress out of synch 20 Table 13 - DIRECTION code assignment 26 Table 14 CK_SEL[3:0] input pin encoding 38 Table 15 - Zero margin SPI-3 timing budget 42 Table 16 - Margin check for SPI-3 timing 42 Table 17 - Bit order within an 8-Bit data register 45 Table 18 - Bit order within a 32-Bit data register 45 Table 19 - Bit order within an 8-Bit data register 45 Table 20 - Bit order within a 16-Bit address register 46 Table 21 - Bit order within an 8-Bit control register 46 Table 22 - Module base address Module_base 46 Table 23 - Indirect access block bases for Module A 46 Table 24 - Indirect access block bases for common module 47 Table 25 - Indirect access data registers direct accessed space at 0x30 to 0x33 47 Table 26 - Indirect access address register direct accessed space at 0x34 to 0x35 47 Table 27 - Indirect access control register direct accessed space at 0x3F 47 Table 28 - Error coding table 48 Table 29 - Direct mapped Module A registers 49 Table 30 - Direct mapped other registers 49 Table 31 - SPI-3 data capture control register 0x00 49 Table 32 - SPI-3 data Capture register 0x01 49 Table 33 - SPI-4 data insert control register 0x02 50 Table 34 - SPI-4 data insert register 0x03 50 Table 35 - SPI-4 data capture control registers register 0x04 50 Table 36 - SPI-3 data insert control register 0x05 50 Table 37 - SPI-4 data capture register 0x06 50 Table 38 - SPI-3 data insert register 0x07 50 Table 39 - Software reset register 0x20 in the direct accessed space 51 Table 40 - SPI-4 status register 0x22 in the direct accessed space 51 Table 41 - SPI-4 enable register 0x23 in the direct accessed space 51 Table 42 - Module status register 0x24 in the direct accessed space 52 Table 43 - Module enable register 0x28 in the direct accessed space 52 Table 44 - Primary interrupt status register 0x2C in the direct accessed space 53 Table 45 - Secondary interrupt status register 0x2D in the direct accessed space 53 Table 46 - Primary interrupt enable register 0x2E in the direct accessed space 53 Table 47 - Secondary interrupt enable register 0x2F in the direct accessed space 53 Table 48 - Module A indirect register 54 Table 49 - SPI-3 ingress LP to LID map 55 Table 50 - SPI-3 general configuration register register_offset=0x00 55 Table 51 - SPI-3 ingress configuration register register_offset=0x01 56 Table 52 - SPI-3 ingress fill level register register_offset=0x02 56 Table 53 - SPI-3 ingress max fill level register register_offset=0x03 56 Table 54 - SPI-3 egress LID to LP map 56 Table 55 - SPI-3 egress configuration register register_offset=0x00 57 Table 56 - SPI-4 ingress to SPI-3 egress flow control register register_offset=0x01 57

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

List of Tables Continued

Table 57 - SPI-3 egress test register register_offset=0x02 57 Table 58 - SPI-3 egress fill level register register_offset=0x03 58 Table 59 - SPI-3 egress max fill level register register_offset=0x04 58 Table 60 - LID associated event counters 0x000-0x17F 59 Table 61 - Non LID associated event counters 0x00 - 0x0B 59 Table 62 - Non LID associated interrupt indication register register_offset 0x0c 60 Table 63 - Non LID associated interrupt enable register register_offset 0x0D 60 Table 64 - LID associated interrupt indication register register_offset 0x0E 60 Table 65 - LID associated interrupt enable register register_offset 0x0F 60 Table 66 - Non critical LID associated capture table register_offset 0x10-0x15 61 Table 67 - SPI-3 to SPI-4 critical LID interrupt indication registers register_offset 0x16-0x17 61 Table 68 - SPI-3 to SPI-4 critical LID interrupt enable registers register_offset 0x18-0x19 61 Table 69 - SPI-4 to SPI-3 critical LID interrupt indication registers register_offset 0x1A-0x1B 61 Table 70 - SPI-4 to SPI-3 critical LID interrupt enable registers register_offset 0x1C-0x1D 61 Table 71 - Critical events source indication register register_offset 0x1E 61 Table 72 - SPI-3 ingress packet length configuration register 62 Table 73 - SPI-4 egress port descriptor table 64 entries 62 Table 74 - SPI-4 egress DIRECTION code assignment 62 Table 75 - SPI-3 ingress port descriptor table Block_base 0x1200 62 Table 76 - SPI-3 to SPI-4 PFP register register_offset 0x00 63 Table 77 - NR_LID field encoding 63 Table 78 - SPI-3 to SPI-4 flow control register register_offset 0x01 63 Table 79 - SPI-4 ingress packet length configuration 64 entries configurable 64 Table 80 - SPI-3 egress port descriptor table 64 entries 64 Table 81 - SPI-3 egress DIRECTION code assignment 64 Table 82 - SPI-4 ingress port descriptor tables 64 entries 64 Table 83 - SPI-4 to SPI-3 PFP register 0x00 65 Table 84 - NR_LID field encoding 65 Table 85 -Common Module Module_base 0x8000 indirect register table 66 Table 86 - SPI-4 ingress LP to LID map 256 entries, one per LP 67 Table 87 - SPI-4 ingress calendar_0 256 entries 67 Table 88 - SPI-4 ingress calendar_1 256 entries 67 Table 89 - SPI-4 ingress configuration register 0x00 67 Table 90 - SPI-4 ingress status configuration register register_offset 0x01 68 Table 91 - SPI-4 ingress status register register_offset 0x02 68 Table 92 - SPI-4 ingress inactive transfer port register_offset 0x03 68 Table 93 - SPI-4 ingress calendar configuration register 0x04 to 0x05 69 Table 94 SPI-4 ingress watermark register register_offset 0x06 69 Table 95 - SPI-4 ingress fill level register register_offset 0x07 69 Table 96 - SPI-4 ingress max fill level register register_offset 0x0B 69 Table 97 - SPI-4 ingress diagnostics register register_offset 0x0F 69 Table 98 - SPI-4 ingress DIP-4 error counter register_offset 0x10 70 Table 99 - SPI-4 ingress bit alignment control register register_offset 0x11 70 Table 100 - SPI-4 ingress start up training threshold register register_offset 0x12 70 Table 101 - SPI-4 egress LID to LP map 256 entries 70 Table 102 - SPI-4 egress calendar_0 256 locations 70 Table 103 - SPI-4 egress calendar_1 256 locations 71 Table 104 SPI-4 egress configuration register_0 register_offset 0x00 71 Table 105 - SPI-4 egress configuration register_1 register_offset 0x01 71 Table 106 - SPI-4 egress status register register_offset 0x02 72 Table 107 - SPI-4 egress calendar configuration register Register_offset 0x03 - 0x04 72 Table 108 - SPI-4 egress diagnostics register register_offset 0x05 72 Table 109 - SPI-4 egress DIP-2 error counter register_offset 0x06 72 Table 110 - SPI-4 ingress bit alignment window register register_offset 0x00 73 Table 111 - SPI-4 ingress lane measure register register_offset 0x01 73

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

List of Tables Continued

Table 112 - SPI-4 ingress bit alignment counter register 0x02 to 0x0B 73 Table 113 - SPI-4 ingress manual alignment phase/result register 0x0C to 0x1F 73 Table 114 - SPI -4 egress data lane timing register register_offset 0x2A 73 Table 115 - SPI-4 egress Control Lane Timing register Register_offset 0x2B 74 Table 116 - SPI-4 egress data clock timing register register_offset 0x2C 74 Table 117 - SPI-4 egress status timing register register_offset 0x2D 74 Table 118 - SPI-4 egress status clock timing register register_offset 0x2E 74 Table 119 - PMON timebase control register register_offset 0x00 75 Table 120 - Timebase register register_offset 0x01 75 Table 121 - Clock generator control register register_offset 0x10 75 Table 122 - OCLK and MCLK frequency select encoding 75 Table 123 - GPIO register register_offset 0x20 76 Table 124 - GPIO monitor table 5 entries 0x21-0x25 for GPIO[0] through GPIO[4] 76 Table 125 - Version number register register_offset 0x30 76 Table 126 JTAG instructions 77 Table 127 maximum ratings 77 Table 128 Recommended Operating Conditions 77 Table 129 Terminal Capacitance 78 Table 130 Thermal Characteristics 78 Table 131 DC Electrical characteristics 79 Table 132 SPI-3AC Input / Output timing specifications 80 Table 133 SPI-4.2 LVDSAC Input / Output timing specifications 82 Table 134 SPI-4 LVTTL status AC Characteristics 82 Table 135 REF_CLK clock input 82 Table 136 OCLK[3:0] clock inputs and MCLK internal clock 82 Table 137 Microprocessor interface 82 Table 138 Microprocessor parallel port Motorola read timing 83 Table 139 Microprocessor parallel port Motorola write timing 84 Table 140 Microprocessor parallel port Intel mode read timing 85 Table 141 Microprocessor parallel port Intel mode write timing 86 Table 142 Microprocessor serial peripheral interface timing 87

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

Exchange between optical ports and NPU/Traffic Manager

INDUSTRIAL TEMPERATURE RANGE

OC-48/
4xOC-12/
16xOC-3

Multi-Rate SONET

SPI-3 IDT88P8341 SPI-4

Framer
6372 drw02

Control Processor

Figure Typical application optical port and NPU/Traffic Manager

INTRODUCTION

The IDT88P8341 device is a SPI-3 to SPI-4 exchange intended for use in optical line cards, Ethernet transport, and multi-service switches. The SPI3 and SPI-4 interfaces are defined by the Optical Interworking Forum.

The device can be used as a rate adapter, a switch, or an aggregation device between network processor units, multi-gigabit framers and PHYs, and switch fabric interface devices.

DATA PATH OVERVIEW

Figure Data Path Diagram shows an overview of the data path through the device.

In normal operation, there are two paths through the IDT88P8341 device the SPI-3 ingress to SPI-4 egress path, and the SPI-4 ingress to SPI-3 egress path. SPI-3 and SPI-4 burst sizes are separately configurable.

In the SPI-3 ingress to SPI-4 egress path, data enter in fragments on the SPI3 interface and are received by the SPI-3 interface block. The fragments are mapped to a SPI-4 address and stored in memory allocated at the SPI-3 level until such a time that the Packet Fragment Processor determines that they are to be transmitted on the SPI-4 interface. The data is transferred in bursts, in line with the OIF SPI-4 implementation agreement, to the SPI-4 interface block, and are transmitted on the SPI-4 interface.

In the SPI-4 ingress to SPI-3 egress path, data enter in bursts on the SPI-4 interface and are received by the SPI-4 interface block. The SPI-4 address is translated to a SPI-3 address, and the data contained in the bursts are stored in memory allocated at the SPI-3 level until such a time that the Packet Fragment Processor determines that they are to be transmitted on the SPI-3 interface. The data is transferred in packet fragments, in line with the OIF SPI-3 implementation agreement, to the SPI-3 interface block, and are transmitted on the SPI-3 interface.
• Eight ADR signals supported for PTPA in packet-level mode - Address range 0 to 255 with support for 64 simultaneously active logical ports - Fragment length section configurable from 16 to 256 bytes in 16 byte multiples - Configurable standard and non-standard bit ordering

SPI-3 implementation features The following are implemented per SPI-3 interface, and there are two
instantiations per device. - Link / PHY layer device - Packet / byte level FIFO status information - Physical port enable - Width of data bus 32 bit or 8 bit - Parity selection odd or even - Enable parity check

SPI-3 ingress The following are implemented per SPI-3 interface, and there are 4
instantiations per device. - SPI-3 LP to Link Identifier LID map - 256 entries, one per SPI-3 LP address - LP enable control - Only 64 of these entries are to be in the active state simultaneously

Backpressure enable
- Link mode only - Enables the assertion of the I_ENB when at least one active LID can not accept data - If not enabled, the I_ENB signal will never be asserted in Link mode, possibly leading to fragments being discarded.

Minimum packet length
- Packets shorter than the minimum length will be optionally counted in the short packet counter.
- Range 0 255 in 1 byte increments

SPI-3 ingress interface Multiple independent data streams can be transmitted over the physical SPI-
3 port. Each of those data streams is identified by a SPI-3 logical port LP Data from a transfer on a SPI-3 logical port and the associated descriptor fields are synchronized to the configurable internal buffer segment pool.

Normal operation

Refer to Glossary] for details about the SPI-3 interface.
• A SPI-3 interface a physical port is enabled by the SPI-3_ENABLE flag
in the SPI-3 configuration register. A disabled interface tri-states all output pins and does not respond to any input signals.
• The interface is configured in PHY or Link layer mode by the LINK flag in the SPI-3 general configuration register.
• at most 64 logical ports can be configured.
• The SPI-3 interface supports data transport over either a 32 bit data interface or over one single 8 bit interface data[7:0] only. The selection is defined by the BUSWIDTH flag in the SPI-3 general configuration register.
• The SPI-3 interface is configured in byte mode or packet mode by the PACKET flag in the SPI-3 general configuration register.
• The SPI-3 interface supports over-clocking.
• Parity checking over data[31:0] is enabled by the PARITY_EN flag in the Table 50, SPI-3 general configuration register register_offset=0x00 . The parity type is defined by the EVEN_PARITY flag. Parity check results over the in-band port address and the data of a transfer are forwarded towards the packet fragment processor.
• SPI Exchange supports zero clock interval spacing between transfers.

SPI-3 ingress interface errors

Given an I_FCLK within specification, the SPI-3 will not dead lock due to any combination or sequence on the SPI-3 interface. The SPI Exchange detects for incorrect SOP / EOP sequences on a logical port. The following sequences are detected:

Successive SOP- SOP sequence rather than SOP Successive EOP- EOP sequence rather than SOP Detection of an illegal sequence results in the generation of an SPI-3 illegal SOP sequence event or SPI-3 illegal EOP sequence even generated. The event is associated to the physical port. The event is directed towards the PMON & DIAG module. A clock available process detects a positive I_FCLK within a 64 MCLK clock cycle period. The result of this process is reported in the I_FCLK_AV flag in the Table 52 SPI-3 ingress fill level register Block_base 0x0200 + Register_offset 0x02 . A status change from the clock available status to the clock not available status generates a maskable SPI-3 ingress clock unavailable interrupt indication, SPI3_ICLK_UN, in Table 62-Non LID associated interrupt indication register Block_Base 0x0C00 + Register_offset 0x0C .

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

SPI-3 ingress Link mode

Refer to [Glossary] for details about the SPI-3 interface.
• The PHY pushes data into the device in blocks from 1 up to 256 bytes.
• The SPI Exchange provides backpressure for the SPI-3 ingress physical
interface by the I_ENB signal. The I_ENB is asserted when at least one
active LID can not accept data. This feature is enabled by the BACKPRESSURE_EN flag in the SPI-3 ingress configuration register register_offset = 0x01 . When the flag is cleared the I_ENB signal will not be asserted, hence no backpressure can be generated.

I_ERR I_Data[31:0] I_PRTY RVAL I_SOP I_EOP I_RSX I_MOD[1:0] I_ENB

IDT88P8341 LINK MODE

I_FCLK

Figure Link mode SPI-3 ingress interface
6372 drw04

SPI-3 ingress PHY mode

The SPI Exchange indicates to the Link layer it has buffer space available by proper response to either Link layer polling packet mode or direct indication on DTPA signals byte mode . The selection is made by the PACKET flag in the SPI-3 configuration register.
• In packet mode the device responds to polling by Link layer device
•
[3:0]

DTPA[3:0] STPA PTPA ADDR[7:0]
byte mode packet mode

LINK

I_ERR I_Data[31:0] I_PRTY

IDT88P8341 PHY MODE

I_SOP I_EOP I_RSX I_MOD[1:0] I_ENB

I_FCLK
SPI-3 ingress LID associated control

Each LID on the SPI-3 interface has the ability to be programmed for minimum and maximum packet length. The minimum packet length can be set from 0 to 255 bytes in one byte increments. The maximum packet length can be set from 0 to 16,383 bytes in one byte increments. Each LID can be enabled and disabled independently.
[LP] = LID | EN | BRV LID

EN BRV

Figure SPI-3 ingress LP to LID map
256 LPs
6372 drw15

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

SPI-4 egress interface port associated control

The SPI-4 interface has an associated LID to LP map See Table 101 - SPI4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF for the purpose of directing the packet fragments from the selected SPI-3 ingress main memory buffer segment pool to the SPI-4 egress interface. The SPI-4 LID map has 256 entries, one per LID. The SPI-4 interface has an enable bit. The burst length is associated with the SPI-4 interface. The allowed burst range is 16 to 256 bytes per burst. The last burst of a packet can be shorter than the programmed burst size.

SPI-4 egress LID associated control

Each of the 256 entries in the SPI-4 egress LID to LP map See Table 101 - SPI-4 egress LID to LP Map 256 entries is used to control the pulling of bursts out of the buffer segment pool and into the SPI-4 egress interface. Each LID can be enabled and disabled independently.
[LID] = LP | EN
256 LIDs

LP Logical Port EN LP Enable
6372 drw16

Figure SPI-4 egress LID to LP map

The diagram below shows the datapath through the device from the SPI3 ingress interface to the SPI-4 egress interface.

SPI-3 8 bit / 32 bit Min 19.44MHz Max 133MHz

Interface Block

Interface Block

JTAG
uproc Chip Counters Memory

LID Counters Memory

Main Memory

SPI-3 / LID map

SPI-4.2 Min 80 MHz Max:400 MHz

SPI-4 / LID map
6372 drw17

Figure SPI-3 ingress to SPI-4 egress datapath 28

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

SPI-3 ingress to SPI-4 egress flow control For control information there are two separate cases to consider The case
that the SPI-3 physical interface port is configured in Link mode, and the case that the SPI-3 is configured in PHY mode. Note that since the SPI-3 physical interfaces are configured separately, the device is able to deal with the case that some of the LP fragments have been received on a Link layer device SPI-3 interface and some have been received on a PHY layer device SPI-3 interface.

For a device in Link mode the Link device can only control the flow of data through the RENB signal. Two modes of operation are implemented and configurable for flow control on this interface either the data can be allowed to flow freely into the device or the RENB signal will be asserted if a condition arises that one of the LPs is unable to receive another fragment. The first of these modes is considered to have no Link layer device flow control, and the second has Link layer device flow control.

For the no Link flow control mode, any data sent to an LP unable to receive another fragment will cause an LP overflow.

For a device in Link mode the Link has complete knowledge of the fill level of the data buffers in each of the LPs in the PHY. This knowledge is attained either through byte level polling or packet level polling.

Both in Link and PHY modes, the data is collected to buffer segments associated with an LP. The SPI-4 PFP is updated with the number of free segments available to the LP. The SPI-4 PFP determines which LP to service based on two factors whether the LP contains enough data for a burst, and the starving / hungry / satisfied state of the LP. For details on the mapping of LPs to LIDs, refer to Table 101 - SPI-4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF.
Direct register format All direct register accesses are one byte. The bit ordering for the direct
access registers is shown. TABLE 17 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER

Direct Register Format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

Bit 7 is the most significant data bit.

Indirect register format The internal format for 32 and 8 bit registers is shown below. The registers
are accessed from the external processor interface as successive bytes of indirect data. The indirect register space includes 32-bit data registers and 8bit data registers. The directly-addressed register space includes directlyaddressable 8-bit data registers, four 8-bit data registers for indirect data access, two 8-bit address registers for indirect data access, and an 8-bit control register

TABLE 18 - BIT ORDER WITHIN A 32-BIT DATA REGISTER

Indirect Data register 0x33

Indirect Data register 0x32

Indirect Data Indirect Data register 0x31 register 0x30
bit 25
bit 16
bit 8
bit 0

Bit 31 is the most significant data bit.

TABLE 19 - BIT ORDER WITHIN AN 8-BIT DATA REGISTER Indirect Data register 0x30 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

Bit 7 is the most significant data bit.
6372 drw29

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

TABLE 20 - BIT ORDER WITHIN A 16-BIT ADDRESS REGISTER

Indirect High Address register 0x35

Indirect Low Address register 0x34
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

Bit 15 is the most significant data bit.

TABLE 21 - BIT ORDER WITHIN AN 8-BIT CONTROL REGISTER

Indirect Control register 0x3F bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0

Bit 7 is the most significant data bit.

INDUSTRIAL TEMPERATURE RANGE

Module base address Module_base There are two modules defined for indirect data access.

TABLE 22 - MODULE BASE ADDRESS MODULE_BASE

MODULE

Module_base

Module A SPI3-A, PFP-A, PMON-A
0x0000

Common SPI-4, timing, PMON, clock, GPIO, and version number
0x8000

Block base There are block bases defined for SPI-3 modules and also for Common, as
shown in the following tables.

TABLE 23 - INDIRECT ACCESS BLOCK BASES FOR MODULE A

Block_base 0x0000 0x0200 0x0500 0x0700 0x0A00 0x0C00 0x1000 0x1100 0x1200 0x1300 0x1600 0x1700 0x1800 0x1900
PACKET A SPI-3 interface can be used either in BYTE or PACKET modes. A SPI-3 interface acting as a Link layer device can poll the attached PHY device for up to 64 LPs if the attached PHY device supports the polling interface. When attached to a PHY device that only supports byte mode, the four direct status indicators can be used. When the SPI Exchange is in PHY mode, the PACKET bit is used to select either a polled or direct status response to the attached Link device.
0 = BYTE mode with direct status indication for up to 4 LPs [3:0] 1= PACKET mode with polled status for up to 64 LPs

SPI3_ENABLE to the state programmed into this bit. A port should be disabled to save power if it is not used.
0=SPI-3 Physical port disabled, outputs are in tristate 1=SPI-3 Physical port enabled

BUSWIDTH The SPI-3 interface can be used as either a single 8-bit or 32-bit interface, according to the needs of the attached device. The SPI-3 ingress and egress of a given SPI-3 physical port will always be of the same bus width.
0=32 bit SPI-3 interface 1=8 bit SPI-3 interface

EVEN_PARITY The SPI-3 interface is provisioned to generate and to check for odd or even parity. The PARITY_EN bit must be set for this to become effective. Odd parity is standard for SPI-3 interfaces.

APRIL 10, 2006

IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE
0=Odd parity on this port 1=Even parity on this port

PARITY_EN generation and checking, according to the state of the EVEN_PARITY bit.
0=Disable parity on this SPI-3 port 1=Enable parity on this SPI-3 port

WATERMARK The SPI-3 interface can be set to a SPI-3 ingress port watermark value. The value of 0x10 is the highest watermark that can be set, meaning all ingress buffers will be full before backpressure will be initiated on the SPI-3 ingress interface. The WATERMARK field value of 0x08 is used to set the watermark for a half-full ingress buffer before tripping backpressure. The units of WATERMARK are one-sixteenth of the available ingress buffering per unit. Each unit is equal to 128 bytes. BACKPRESSURE_EN must be set [Register_offset 0x01] for the watermark to become effective. The watermark field is usually set to 0x10, and the FREE_SEGMENT field of Table 75, SPI3 ingress port descriptor tables Block_base 0x1200 is used for per LID backpressure.

SPI-3 ingress fill level register Block_base 0x0200
+ Register_offset 0x02

TABLE 52 - SPI-3 INGRESS FILL LEVEL REGISTER REGISTER_OFFSET=0x02

Field

Bits Length Initial Value

FILL_CUR
0x00

I_FCLK_AV

There is one register for SPI-3 ingress fill level register for the SPI-3 interface. The register has read-only access. The bit fields of the SPI-3 ingress fill level register are described.

FILL_CUR register, the value read from it will change rapidly and is used for internal diagnostics only.

I_FCLK_AV Current SPI-3 ingress clock availability is checked here. 0=SPI-3 ingress clock not detected on a SPI-3 port 1=SPI-3 ingress clock transitions detected on a SPI-3 port

SPI-3 ingress configuration register Block_base 0x0200 + Register_offset 0x01

TABLE 51 - SPI-3 INGRESS CONFIGURATION

REGISTER REGISTER_OFFSET=0x01

Field

Bits Length Initial Value

BACKPRESSURE_EN

FIX_LP

Reserved
31:2
0x0000

There is one SPI-3 ingress configuration register for the SPI-3 interface. The
register has read and write access.

The bit fields for the SPI-3 ingress configuration register are described in the
following paragraphs.

BACKPRESSURE_EN the SPI-3 interface can have backpressure enabled or disabled. Disabling backpressure means that data coming into the ingress may be lost if the SPI-3 interface ingress buffers overflow. The SPI-3 interface can run at full-rate, however, since there will be no backpressure. Attached devices that do not respond properly to backpressure should be interfaced by disabling backpressure.

Enabling backpressure will cause the I_ENB signal to be asserted when the ingress buffer fill level is equal to the WATERMARK value [Register_offset 0x00], or the free segment buffer threshold Table 75, SPI-3 ingress port descriptor table Block_base 0x1200 has been reached for any active LID.
Block base 0x0700 registers

The SPI-4 ingress to SPI-3 egress flow control register has read and write access. The bit fields of the SPI-4 ingress to SPI-3 egress flow control register are described.

CREDIT_EN Theflowcontrolinformationreceivedfrom the attached SPI-3 device is interpreted as status or credit information as selected by the CREDIT_EN bit in the SPI-4 ingress to SPI-3 egress flow control Register. If the status mode is used, data will be egressed until the status is changed by the attached SPI-3 device. If the credit mode is used, the SPI-3 egress will transmit only one packet fragment and then wait for an update in the internal buffer segment pool status before sending another packet fragment.
0=Status mode 1=Credit mode

SPI-3 egress configuration register Block_base
0x0700 + Register_offset 0x00

TABLE 55 - SPI-3 EGRESS CONFIGURATION REGISTER REGISTER_OFFSET=0x00

Field

Bits Length Initial Value

POLL_LENGTH
0x0F

Reserved
0b00

STX_SPACING

EOP_SPACING

Reserved
31:10
0x00

There is one SPI-3 egress configuration register per SPI-3 interface. The

SPI-3 egress configuration registers have read and write access. A SPI-3
egress configuration registers is used to control the poll sequence length of a

SPI-3 egress interface when the SPI-3 interface is in Link mode. The SPI-3
egress configuration register is used to add two cycles to STX or EOP as
required to interface to the attached device.

POLL_LENGTH Link layer poll sequence length when in Link mode. The poll sequence is from the LP associated with LID0 to the LP associated with the LID for POLL_LENGTH -

STX_SPACING This bit is used to enable or disable the adding of two dummy STX cycles to the SPI-3 egress interface to meet the needs of an attached device.
0= No dummy STX cycles are added to the SPI-3 egress. 1= Two dummy STX cycles are added to the SPI-3 egress

EOP_SPACING This bit is used to enable or disable the adding of two dummy EOP cycles to the SPI-3 egress interface to meet the needs of an attached device.
0= No dummy EOP cycles are added to the SPI-3 egress. 1= Two dummy EOP cycles are added to the SPI-3 egress

SPI-4 ingress to SPI-3 egress flow control register Block_base 0x0700 + Register_offset 0x01

TABLE 56 - SPI-4 INGRESS TO SPI-3 EGRESS FLOW CONTROL REGISTER REGISTER_OFFSET=0x01

Field CREDIT_EN BURST_EN LOOP_BACK Reserved

Bits Length Initial Value
31:3
0x00

BURST_EN to an LP. When this feature is not enabled, only one burst per LP is allowed into the SPI-3 egress buffers.
0=Disable burst enable 1=Enable burst enable

LOOP_BACK In this mode the contents of a SPI-3 ingress are directly transferred to a SPI-3 egress buffers of the same port. This mode is useful for off-line diagnostics.
0=Disable loopback 1=Enable loopback

SPI-3 egress test register Block_base 0x0700 +

Register_offset 0x02
05/09/05
• Added sections System Reset and Power on Sequence p.40 .
• Updated PFR to PFP in Table 49 "Module A indirect register" p.53
• Updated Table 80 "SPI-4 ingress packet length configuration" p.63
• Updated length for Reserved in Table 83 "SPI-4 ingress port descriptor" p.63
• Updated Table 87 "SPI-4 ingress LP to LID map" p.66
• Added Green to Ordering information p.94
08/05/05
• Updated Table 128 "Absolute maximum ratings" p.76
10/20/05
• Updated Table 7 "Parallel microprocessor interface" p.12
• Updated Table 131 "Thermal Characteristics" p.77
• Updated Microprocessor parallel port section p.82-85
11/09/05
• Updated Table 126 "Version number register register_offset 0x30 " p.75
12/01/05
• Updated SPI-4 status channel software p.42
01/05/06
• Updated Figure 4 "PHY mode SPI-3 ingress interface" p.14
• Deleted Table 13 "NR_LID Field Encoding". Updated SPI-4 egress queues, Normal operation section p.26
• Updated Section "SPI-4 status channel software" p.42
• Updated Table 26 title "Indirect access address register at 0x34 to 0x35" p.46
• Updated section title "Indirect registers for SPI-3A module" p.53
• Updated Table 127 "Absolute maximum ratings" p.76
• Updated Table 129 "Terminal Capacitance" p.77
04/10/06
• Initial Release of Final Datasheet with new section "Software Eye-Opening Check on SPI-4" & new Figure "DDR interface and eye opening check through over sampling" p.43-44
• Updated Clock generator pg. 38
• Updated SPI-4 ingress watermark register pg. 69
• Updated Clock generator control register pg. 75
• Updated Table 130 Thermal Characteristics pg. 78
• Updated Table 132 SPI-3 AC Input/Output timing specifications pg. 80
• Updated Table 136 OCLK[3:0] outputs and MCLK internal clock pg. 82

APRIL 10, 2006
ORDERING INFORMATION

Device Type

Package

Process / Temperature

Range

Industrial -40C to +85C

Green

Plastic Ball Grid Array PBGA, BH820-1

NOTE Green parts are available.
88P8341

SPI Exchange SPI-3 to SPI-4
6372 drw38

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1716
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 88P8341BHGI Datasheet file may be downloaded here without warranties.

Datasheet ID: 88P8341BHGI 637398