IDT74ALVCHR16601PAG8
IDT74ALVCHR16601PAG8 Datasheet
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
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IDT74ALVCHR16601PAG8 |
IDT74ALVCHR16601PAG8 (pdf) |
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| IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCHR16601 BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: • MICRON CMOS Technology • Typical tSK o Output Skew < 250ps • ESD > 2000V per MIL-STD-883, Method 3015 > 200V using machine model C = 200pF, R = 0 • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels W typ. static • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package DRIVE FEATURES: • Balanced Output Drivers ±12mA • Low Switching Noise APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems DESCRIPTION: This 18-bit universal bus transceiver is built using advanced dual metal CMOS technology. The transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. The clock can be controlled by the clock-enable CLKENAB and CLKENBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The ALVCHR16601 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCHR16601 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. FUNCTIONAL BLOCK DIAGRAM OEAB CLKENAB CLKAB LEAB LEBA 28 CLKBA 30 CLKENBA 29 OEBA 27 1D C1 54 B1 CE 1D C1 CLK TO 17 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 2004 Integrated Device Technology, Inc. JANUARY 2004 DSC-4491/5 IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX ALVC X Temp. Range Bus-Hold Family Device Type Package INDUSTRIAL TEMPERATURE RANGE PA Thin Shrink Small Outline Package PAG TSSOP - Green 601 18-Bit Universal Bus Transceiver with 3-State Outputs R16 Double-Density, ±12mA H Bus-Hold 74 -40°C to +85°C CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support: |
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