IDT72V36106L15PF8
IDT72V36106L15PF8 Datasheet
IDT72V3686 IDT72V3696 IDT72V36106
| Part | Datasheet |
|---|---|
IDT72V36106L15PF8 |
IDT72V36106L15PF8 (pdf) |
| Related Parts | Information |
|---|---|
IDT72V36106L10PF |
IDT72V36106L10PF |
IDT72V36106L10PF8 |
IDT72V36106L10PF8 |
IDT72V36106L15PF |
IDT72V36106L15PF |
| PDF Datasheet Preview |
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| VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2 IDT72V3686 IDT72V3696 IDT72V36106 • Memory storage capacity IDT72V3686 16,384 x 36 x 2 IDT72V3696 32,768 x 36 x 2 IDT72V36106 65,536 x 36 x 2 • Clock frequencies up to 100 MHz 6.5ns access time • Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports Port C receives and Port B transmits • 18-bit word and 9-bit byte bus sizing of 18 bits word on Ports B and C • Select IDT Standard timing using EFA , EFB , FFA , and FFC flag functions or First Word Fall Through Timing using ORA, ORB, IRA, and IRC flag functions • Programmable Almost-Empty and Almost-Full flags each has five default offsets 8, 16, 64, 256 and 1024 • Serial or parallel programming of partial flags • Big- or Little-Endian format for word and byte bus sizes • Loopback mode on Port A • Retransmit Capability • Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings • Mailbox bypass registers for each FIFO • Free-running CLKA, CLKB and CLKC may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted • Auto power down minimizes power dissipation • Available in a space-saving 128-pin Thin Quad Flatpack TQFP • Pin compatible to the lower density parts, IDT72V3626/72V3636/ 72V3646/72V3656/72V3666/72V3676 • Industrial temperature range to +85°C is available • Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM CLKA CSA W/RA ENA MBA LOOP MRS1 PRS1 FFA/IRA AFA FS2 FS0/SD FS1/SEN A0-A35 EFA/ORA Port-A Control Logic FIFO1, Mail1 Reset Logic RT1 RTM RT2 FIFO1 and FIFO2 Retransmit Logic MBF2 Mail 1 Register RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 FIFO1 Write Pointer Read Pointer Status Flag Logic Programmable Flag Offset Registers Timing Mode 16 FIFO2 Status Flag Logic Read Pointer Write Pointer RAM ARRAY 36 16,384 x 36 32,768 x 36 65,536 x 36 Mail 2 Register Output Register Input BusMatching Input Register Input Register Output BusMatching Output Register MBF1 B0-B17 Port-B Control Logic CLKB RENB CSB MBB SIZEB Common Port Control Logic B and C EFB/ORB AEB ORDERING INFORMATION Device Type Power Speed Package Process/ Temperature Range BLANK Commercial 0oC to +70oC Green Thin Quad Flat Pack TQFP, PK128-1 10 15 Commercial Only Clock Cycle Time tCLK Speed in Nanoseconds Low Power 72V3686 16,384 x 36 x 2 3.3V Triple Bus SyncFIFO with Bus-Matching 72V3696 32,768 x 36 x 2 3.3V Triple Bus SyncFIFO with Bus-Matching 72V36106 65,536 x 36 x 2 3.3V Triple Bus SyncFIFO with Bus-Matching 4676 drw 39 NOTES Industrial temperature range is available by special order. Green parts available. For specific speeds and packages contact your sales office. DATASHEET DOCUMENT HISTORY 11/08/2000 pgs. 1, 7, 9, 10, 13, 22 and 39 12/14/2000 pgs. 5 and 03/27/2001 pgs. 7 and 11/04/2003 05/23/2008 pgs. 1, 7, and 02/05/2009 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email: |
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