IDT72T54262L6-7BB

IDT72T54262L6-7BB Datasheet

IDT72T54242 IDT72T54252 IDT72T54262

Part	Datasheet
IDT72T54262L6-7BB	IDT72T54262L6-7BB (pdf)

Related Parts	Information
IDT72T54262L5BB	IDT72T54262L5BB
IDT72T54262L6-7BBI	IDT72T54262L6-7BBI
IDT72T54262L5BBG	IDT72T54262L5BBG

PDF Datasheet Preview
2.5V QUAD/DUAL TeraSync DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS 32,768 x 10 x 4/16,384 x 20 x 2 65,536 x 10 x 4/32,768 x 20 x 2 131,072 x 10 x 4/65,536 x 20 x 2 IDT72T54242 IDT72T54252 IDT72T54262 • Choose from among the following memory organizations IDT72T54242 - 32,768 x 10 x 4/32,768 x 10 x 2 IDT72T54252 - 65,536 x 10 x 4/65,536 x 10 x 2 IDT72T54262 - 131,072 x 10 x 4/131,072 x 10 x 2 • User Selectable Quad / Dual Mode - Choose between two or four independent FIFOs • Quad Mode offers - Eight discrete clock domain, four write clocks & four read clocks - Four separate write ports, write data to four independent FIFOs - 10-bit wide write ports - Four separate read ports, read data from any of four independent FIFOs - Independent set of status flags and control signals for each FIFO • Dual Mode offers - Four discrete clock domain, two write clocks & two read clocks - Two separate write ports, write data to two independent FIFOs - 10-bit/20-bit wide write ports - Two separate read ports, read data from any of two independent FIFOs - Independent set of status flags and control signals for each FIFO - Bus-Matching on read and write port x10/x20 - Maximum depth of each FIFO is the same as in Quad Mode • Up to 200MHz operating frequency or 2Gbps throughput in SDR mode • Up to 100MHz operating frequency or 2Gbps throughput in DDR mode • Double Data Rate, DDR is selectable, providing up to 400Mbps bandwidth per data pin • User selectable Single or Double Data Rate modes on both the write port s and read port s • All I/Os are LVTTL/ HSTL/ eHSTL user selectable • 3.3V tolerant inputs in LVTTL mode • ERCLK and EREN Echo outputs on all read ports • Write enable WEN and Chip Select WCS input for each write port • Read enable REN and Chip Select RCS input for each read port • User Selectable IDT Standard mode using EF and FF or FWFT mode using IR and OR • Programmable Almost Empty and Almost Full flags per FIFO • Dedicated Serial Port for flag offset programming • Power Down pin minimizes power consumption • 2.5V Supply Voltage • Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm • IEEE compliant JTAG port provides boundary scan function • Low Power, High Performance CMOS technology • Industrial temperature range -40°C to +85°C • Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAMS Quad Mode FIFO 0 WCLK0 WEN0 WCS0 Data In D[9:0] x10 FIFO 1 WCLK1 WEN1 WCS1 Data In D[19:10] x10 FIFO 2 WCLK2 WEN2 WCS2 Data In D[29:20] x10 FIFO 3 WCLK3 WEN3 WCS3 Data In D[39:30] x10 32,768 x 10 65,536 x 10 131,072 x 10 FIFO 0 32,768 x 10 65,536 x 10 131,072 x 10 FIFO 1 32,768 x 10 65,536 x 10 131,072 x 10 FIFO 2 32,768 x 10 65,536 x 10 131,072 x 10 RCLK0 REN0 RCS0 OE0 ERCLK0 EREN0 FIFO 0 Q[9:0] Data Out RCLK1 REN1 RCS1 ERCLK1 EREN1 FIFO 1 Q[19:10] Data Out RCLK2 REN2 RCS2 OE2 ERCLK2 EREN2 FIFO 2 Q[29:20] Data Out RCLK3 REN3 RCS3 ERCLK3 ORDERING INFORMATION Device Type X Power XX Speed XX Package Process / Temperature Range BLANK I 1 5 6-7 Commercial 0°C to +70°C Industrial -40°C to +85°C Green Plastic Ball Grid Array PBGA, BB324-1 Commercial Only Clock Cycle Time tCLK Commercial and Industrial Speed in Nanoseconds Low Power 72T54242 72T54252 72T54262 32,768 x 10 x 4/32,768 x 10 x 2.5V Quad/Dual TeraSyncTM DDR/SDR FIFO 65,536 x 10 x 4/65,536 x 10 x 2.5V Quad/Dual TeraSyncTM DDR/SDR FIFO 131,072 x 10 x 4/131,072 x 10 x 2.5V Quad/Dual TeraSyncTM DDR/SDR FIFO 6158 drw41 NOTES Industrial temperature range product for the 6-7 speed grade is available as a standard device. All other speed grades available by special order. Green parts available. For specific speeds contact your sales office. DATASHEET DOCUMENT HISTORY 12/01/2003 pgs. 1, 6, 13, 27, and 03/22/2005 pgs. 1, 4, 7, 12-15 and 02/11/2009 pgs. 1 and CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email:

PDF Datasheet Preview

2.5V QUAD/DUAL TeraSync DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS 32,768 x 10 x 4/16,384 x 20 x 2 65,536 x 10 x 4/32,768 x 20 x 2 131,072 x 10 x 4/65,536 x 20 x 2

IDT72T54242 IDT72T54252 IDT72T54262
• Choose from among the following memory organizations IDT72T54242 - 32,768 x 10 x 4/32,768 x 10 x 2 IDT72T54252 - 65,536 x 10 x 4/65,536 x 10 x 2 IDT72T54262 - 131,072 x 10 x 4/131,072 x 10 x 2
• User Selectable Quad / Dual Mode - Choose between two or four independent FIFOs
• Quad Mode offers - Eight discrete clock domain, four write clocks & four read clocks - Four separate write ports, write data to four independent FIFOs - 10-bit wide write ports - Four separate read ports, read data from any of four independent FIFOs - Independent set of status flags and control signals for each FIFO
• Dual Mode offers - Four discrete clock domain, two write clocks & two read clocks - Two separate write ports, write data to two independent FIFOs - 10-bit/20-bit wide write ports - Two separate read ports, read data from any of two independent FIFOs - Independent set of status flags and control signals for each FIFO - Bus-Matching on read and write port x10/x20 - Maximum depth of each FIFO is the same as in Quad Mode
• Up to 200MHz operating frequency or 2Gbps throughput in SDR mode
• Up to 100MHz operating frequency or 2Gbps throughput in DDR mode
• Double Data Rate, DDR is selectable, providing up to 400Mbps
bandwidth per data pin
• User selectable Single or Double Data Rate modes on both the
write port s and read port s
• All I/Os are LVTTL/ HSTL/ eHSTL user selectable
• 3.3V tolerant inputs in LVTTL mode
• ERCLK and EREN Echo outputs on all read ports
• Write enable WEN and Chip Select WCS input for each write port
• Read enable REN and Chip Select RCS input for each read port
• User Selectable IDT Standard mode using EF and FF or FWFT
mode using IR and OR
• Programmable Almost Empty and Almost Full flags per FIFO
• Dedicated Serial Port for flag offset programming
• Power Down pin minimizes power consumption
• 2.5V Supply Voltage
• Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm
• IEEE compliant JTAG port provides boundary scan function
• Low Power, High Performance CMOS technology
• Industrial temperature range -40°C to +85°C
• Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAMS

Quad Mode

FIFO 0

WCLK0 WEN0 WCS0

Data In D[9:0] x10

FIFO 1

WCLK1 WEN1 WCS1

Data In D[19:10] x10

FIFO 2

WCLK2 WEN2 WCS2

Data In D[29:20] x10

FIFO 3

WCLK3 WEN3 WCS3

Data In D[39:30] x10
32,768 x 10 65,536 x 10 131,072 x 10

FIFO 0
32,768 x 10 65,536 x 10 131,072 x 10

FIFO 1
32,768 x 10 65,536 x 10 131,072 x 10

FIFO 2
32,768 x 10 65,536 x 10 131,072 x 10

RCLK0

REN0 RCS0 OE0

ERCLK0 EREN0

FIFO 0

Q[9:0] Data Out

RCLK1

REN1

RCS1

ERCLK1

EREN1

FIFO 1

Q[19:10] Data Out

RCLK2 REN2 RCS2 OE2 ERCLK2 EREN2

FIFO 2

Q[29:20] Data Out

RCLK3

REN3

RCS3

ERCLK3
ORDERING INFORMATION

Device Type

X Power

XX Speed

XX Package

Process / Temperature

Range

BLANK I 1
5 6-7

Commercial 0°C to +70°C Industrial -40°C to +85°C

Green Plastic Ball Grid Array PBGA, BB324-1

Commercial Only

Clock Cycle Time tCLK

Commercial and Industrial Speed in Nanoseconds

Low Power
72T54242 72T54252 72T54262
32,768 x 10 x 4/32,768 x 10 x 2.5V Quad/Dual TeraSyncTM DDR/SDR FIFO 65,536 x 10 x 4/65,536 x 10 x 2.5V Quad/Dual TeraSyncTM DDR/SDR FIFO 131,072 x 10 x 4/131,072 x 10 x 2.5V Quad/Dual TeraSyncTM DDR/SDR FIFO
6158 drw41

NOTES Industrial temperature range product for the 6-7 speed grade is available as a standard device. All other speed grades available by special order. Green parts available. For specific speeds contact your sales office.

DATASHEET DOCUMENT HISTORY
12/01/2003
pgs. 1, 6, 13, 27, and
03/22/2005
pgs. 1, 4, 7, 12-15 and
02/11/2009
pgs. 1 and

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1753
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72T54262L6-7BB Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT72T54262L6-7BB 637357