STDP4028AB
STDP4028AB Datasheet
STDP4028 DisplayPort transmitter
| Part | Datasheet |
|---|---|
STDP4028AB |
STDP4028AB (pdf) |
| PDF Datasheet Preview |
|---|
| STDP4028 DisplayPort transmitter Datasheet MegaChips’ Proprietary Information MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips does not assume any responsibility or liability arising out of application or use of any product or service described herein except as explicitly agreed upon. MegaChips’ Proprietary Information Page 1 of 43 STDP4028 • Enhanced DP transmitter DP 1.1a compliant Embedded DisplayPort eDP compliant 1, 2, or 4 lanes • Higher bandwidth “Turbo mode” Gbps per lane, supports 1920 x 1080 FHD 120 Hz/10-bit color video standard timings and Ch audio 2560 x 1600 WQXGA , 2560 x 2048 QSXGA 60 Hz/10-bit color graphics and Ch audio • Interface compatibility with wide range of display controller ICs LVTTL 60 wide and LVDS quad bus video interface 8-Ch I2S and SPDIF audio interface • Robust AUX channel Link service, maintenance I2C-over-AUX MCCS, DDC IR, full duplex UART protocol • Configurable through I2C host interface • Supports HDCP with on-chip keys • HDCP repeater capability Acts as downstream transmitter • Spread spectrum on DisplayPort, LVDS, and TTL interfaces for EMI reduction • Supports deep color and color format conversion RGB/YUV 4:4:4 10-bit color YUV 4:2:2/4:2:0 12-bit color RGB 4:4:4 to YUV 4:4:4 conversion and vice-versa • Low power operation 18 mW standby • I2C to AUX bridge for EDID, MCCS pass through • Supports HBR/“Turbo” speed over HBR/RBR- rated long cables 15 m and more • Package 164 LFBGA 12 x 12 mm / mm • Power supply voltages V I/O V core • Digital TV, docking station, STB, game console, etc. QLVDS/ TTL 60 Video I2S/SPDIF Audio LVDS/TTL Receiver I2S/SPDIF Receiver DisplayPort Transmitter DP Output I2C Host Crystal Interface Oscillator GPIO I2C Master C4028-DAT-01p MegaChips’ Proprietary Information Page 2 of 43 Contents STDP4028 Description 6 Application overview 7 Feature attributes 8 BGA footprint and pin lists 9 Ball grid array diagram 9 Ordering information 41 C4028-DAT-01p MegaChips’ Proprietary Information Page 3 of 43 List of Tables STDP4028 Table C4028-DAT-01p MegaChips’ Proprietary Information Page 4 of 43 List of Figures STDP4028 Figure System interface block diagram 7 Pin diagram. 10 Package specification 26 Marking template 27 Digital video input timing 31 LVDS single-ended waveform 33 Receiver strobe positions LVDS input 33 Receiver margins 34 Digital audio I2S input timing 35 I2C Timing 38 SPI output or serial interface SPI ROM input timing 39 SPI input or serial interface SPI ROM output timing 40 C4028-DAT-01p MegaChips’ Proprietary Information Page 5 of 43 STDP4028 The STDP4028 is a DisplayPort transmitter IC for the secure transmission of high-bandwidth, uncompressed digital audio-video signals targeted for applications such as DTV, LCD monitor, docking station, STB and other types of consumer audio-video systems. STDP4028 is VESA DP 1.1a and eDP compliant device, implementing a single link DisplayPort output port comprising four main lanes, auxiliary channel, and HPD. In addition to the standard HBR Gbps and RBR Gbps speeds, this device supports “turbo” speed of Gbps per lane with a total link bandwidth of Gbps. The higher bandwidth provides unique benefits to users over other commercial DP transmitters for embedded applications by offering additional margin to support higher color depth, resolution, and refresh rate. For example, STDP4028 supports FHD non-reduced blanking video 1080p 30-bit color per pixel at 120 Hz, plus Ch audio in two-box TV applications. The high-speed auxiliary channel in STDP4028 acts as a bidirectional communication link, supporting application-specific protocols such as MCCS, DDC, UART, IR, as well as, the dedicated DisplayPort link training and device management functions. The STDP4028 supports RGB and YUV video color formats with color depth of 12 YUV 4:2:2 only , 10, and 8 bits. This device offers LVDS and LVTTL input interface configurable to map a wide range of display controller products. The Quad LVDS interface supports video signals up to 400 MHz pixel rate with flexible channel and lane swapping options. The 60-bit LVTTL input ports on STDP4028 can be mapped to transfer video data either in two pixels per clock or single pixel per clock of a chosen color depth. The STDP4028 also supports both compressed and uncompressed audio formats. This device comprises four I2S audio inputs, supporting up to 8 channels LPCM audio and a single wire SPDIF input for encoded audio. The STDP4028 features HDCP content protection scheme with an embedded key option for secure transmission of digital audio-video content. In addition, it supports the HDCP repeater function and, thus acts as a downstream transmitter suitable for two-box TV and HDMI/DVI to DP converter applications.The STDP4028 is configurable from an external host through the I2C host interface. This IC also includes general-purpose inputs/outputs for controlling system components. The STDP4028 features a color space converter RGB to YUV and YUV to RGB for flexible interface with external video processing devices. C4028-DAT-01p MegaChips’ Proprietary Information Page 6 of 43 STDP4028 Application overview The STDP4028 is designed as DisplayPort transmitter device for transferring high bandwidth video and audio in PC and CE applications. Typical audio-video source system has a graphics or video processing device that acts as system master host . The host controller configures STDP4028 through an I2C host interface. The host and STDP4028 also use interrupt mechanism whenever the slave needs attention. The STDP4028 may require an external SPI Flash to store firmware for supporting custom specific applications. The audio and video signal from the host controller is converted in to DisplayPort streams through STDP4028 and transfer to an external display system over standard DisplayPort cable. The I2C to AUX bypass channel handles the I2C traffic between STDP4028 and host controller as shown in the figure below. Figure System interface block diagram Flash SPI Flash I2C Master Host Controller INTR TTL 60 bit HS, VS, CLK, DE I2S/SPDIF I2C slave STDP4028 Main Link AUX CH HPD_in Ordering information STDP4028-AB Table Order codes Description 164 LFBGA 12 x 12 mm STDP4028 C4028-DAT-01p MegaChips’ Proprietary Information Page 41 of 43 Date 03-Mar-2016 Changes Initial release. STDP4028 C4028-DAT-01p MegaChips’ Proprietary Information Page 42 of 43 STDP4028 Notice Semiconductor products may possibly experience breakdown or malfunction. Adequate care should be taken with respect to the safety design of equipment in order to prevent the occurrence of human injury, fire or social loss in the event of breakdown or malfunction of semiconductor products The overview of operations and illustration of applications described in this document indicate the conceptual method of use of the semiconductor product and do not guarantee operability in equipment in which the product is actually used. The names of companies and trademarks stated in this document are registered trademarks of the relevant companies. MegaChips Co. provides no guarantees nor grants any implementation rights with respect to industrial property rights, intellectual property rights and other such rights belonging to third parties or/and MegaChips Co. in the use of products and of technical information including information on the overview of operations and the circuit diagrams that are described in this document. The product described in this document may possibly be considered goods or technology regulated by the Foreign Currency and Foreign Trade Control Law. In the event such law applies, export license will be required under said law when exporting the product. This regulation shall be valid in Japan domestic. In the event the intention is to use the product described in this document in applications that require an extremely high standard of reliability such as nuclear systems, aerospace equipment or medical equipment for life support, please contact the sales department of MegaChips Co. in advance. All information contained in this document is subject to change without notice. Copyright 2016 MegaChips Corporation All rights reserved MegaChips Corporation Head Quarters 1-1-1 Miyahara, Yodogawa-ku Osaka 532-0003, Japan TEL +81-6-6399-2884 MegaChips Corporation Tokyo Office 17-6 Ichiban-cho, Chiyoda-ku, Tokyo 102-0082, Japan TEL +81-3-3512-5080 MegaChips Corporation Makuhari Office 1-3 Nakase Mihama-ku Chiba 261-8501, Japan TEL +81-43-296-7414 MegaChips Corporation San Jose Office 2033 Gateway Place, Suite 400, San Jose, CA 95110 U.S.A. TEL +1-408-570-0555 MegaChips Corporation India Branch 17th Floor, Concorde Block UB City, Vittal Mallya Road, Bangalore 560-001, India TEL +91-80-4041-3999 MegaChips Corporation Taiwan Branch RM. B 2F, Worldwide House, No.129, Min Sheng E. Rd., Sec. 3, Taipei 105, Taiwan TEL +886-2-2547-1297 MegaChips Corporation Tainan Office RM. 2, 8F, No.24, Da Qiao 2 Rd., Yong Kang Dist., Tainan 710, Taiwan TEL +886-6-302-2898 MegaChips Corporation Zhunan Office No.118, Chung-Hua Rd., Chu-Nan, Miao-Li 350, Taiwan TEL +886-37-666-156 MegaChips Corporation Shenzhen Office Room 6307, Office Tower, Shun Hing Square, 5002 Shen Nan Dong Road, Luohu District, Shenzhen 518000, P. R. China TEL +86-755-3664-6990 C4028-DAT-01p MegaChips’ Proprietary Information Page 43 of 43 |
| More datasheets: 402T | PICOASMDC010S-2 | J202_D26Z | J201 | J202_D74Z | J202 | J201_D74Z | J202_D27Z | J201_D27Z | MMBFJ203 |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived STDP4028AB Datasheet file may be downloaded here without warranties.