IDT71V2576S150PFI8

IDT71V2576S150PFI8 Datasheet

IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA

Part	Datasheet
IDT71V2576S150PFI8	IDT71V2576S150PFI8 (pdf)

Related Parts	Information
IDT71V2576S133PFI8	IDT71V2576S133PFI8
IDT71V2576S133PF8	IDT71V2576S133PF8
IDT71V2576S133PF	IDT71V2576S133PF
IDT71V2576S133PFI	IDT71V2576S133PFI
IDT71V2576S150PFI	IDT71V2576S150PFI
IDT71V2576YS150PF	IDT71V2576YS150PF
IDT71V2576YS150PF8	IDT71V2576YS150PF8
IDT71V2576YS150PFG	IDT71V2576YS150PFG
IDT71V2576YS150PFG8	IDT71V2576YS150PFG8
IDT71V2576S150PF8	IDT71V2576S150PF8
IDT71V2576S150PF	IDT71V2576S150PF

PDF Datasheet Preview
128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA 128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial and Industrial 150MHz 3.8ns clock access time 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control GW , byte write enable BWE , and byte writes BWx 3.3V core power supply Power down controlled by ZZ input 2.5V I/O Optional - Boundary Scan JTAG Interface IEEE compliant Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA Pin Description Summary The IDT71V2576/78 are high-speed SRAMs organized as 128K x 36/256K x The IDT71V2576/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a selftimed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V2576/78 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected ADV=LOW , the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and 165 fine pitch ball grid array fBGA . A0-A17 Address Inputs Input Synchronous Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous Output Enable Input Asynchronous Global Write Enable Input Synchronous Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4 1 Individual Byte Write Selects Input Synchronous Clock Input Burst Address Advance Input Synchronous ADSC Address Status Cache Controller Input Synchronous Ordering Information IDT XXX Device Type Power Speed Package Process/ Temperature Range Blank I Commercial 0°C to +70°C Industrial -40°C to +85°C 100-pin Plastic Thin Quad Flatpack TQFP BG BQ 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA 150 133 Frequency in Megahertz Standard Power Standard Power with JTAG Interface Blank Y 71V2576 71V2578 First generation or current stepping Second generation die step , 128K x 36 Pipelined Burst Synchronous SRAM with 2.5V I/O 256K x 18 Pipelined Burst Synchronous SRAM with 2.5V I/O * JTAG SA Version is not available with 100-pin TQFP package 4876 drw 13 Package Information 100-Pin Thin Quad Plastic Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Information available on the IDT website IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges Datasheet Document History 7/23/99 9/17/99 12/31/99 Pg. 8 Pg. 11 Pg. 18 Pg. 20 Pg. 1, 8, 11, 19 04/04/00 Pg. 1, 4, 8, 11, 19 Pg. 18 Pg. 4 06/01/00 07/15/00 10/25/00 04/22/03 06/30/03 Pg. 20 Pg. 7 Pg. 8 Pg. 20 Pg. 8 Pg. 4 Pg. 1,2,3,5-9 Pg. 5-8 Pg. 19,20 Pg. 21-23 Pg. 24 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support 800-345-7015

PDF Datasheet Preview

128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA
128K x 36, 256K x 18 memory configurations Supports high system speed:

Commercial and Industrial 150MHz 3.8ns clock access time 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control GW , byte write enable BWE , and byte writes BWx 3.3V core power supply Power down controlled by ZZ input 2.5V I/O Optional - Boundary Scan JTAG Interface IEEE compliant Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA

Pin Description Summary

The IDT71V2576/78 are high-speed SRAMs organized as 128K x 36/256K x The IDT71V2576/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a selftimed write based upon a decision which can be left until the end of the write cycle.

The burst mode feature offers the highest level of performance to the system designer, as the IDT71V2576/78 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected ADV=LOW , the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin.

The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and 165 fine pitch ball grid array fBGA .

A0-A17

Address Inputs

Input

Synchronous

Chip Enable

Input

Synchronous

CS0, CS1

Chip Selects

Input

Synchronous

Output Enable

Input

Asynchronous

Global Write Enable

Input

Synchronous

Byte Write Enable

Input

Synchronous

BW1, BW2, BW3, BW4 1

Individual Byte Write Selects

Input

Synchronous

Clock

Input

Burst Address Advance

Input

Synchronous

ADSC

Address Status Cache Controller

Input

Synchronous
Ordering Information

IDT XXX

Device Type

Power

Speed

Package Process/ Temperature Range

Blank I

Commercial 0°C to +70°C Industrial -40°C to +85°C
100-pin Plastic Thin Quad Flatpack TQFP

BG BQ
119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA
150 133

Frequency in Megahertz

Standard Power

Standard Power with JTAG Interface

Blank Y
71V2576 71V2578

First generation or current stepping Second generation die step
, 128K x 36 Pipelined Burst Synchronous SRAM with 2.5V I/O
256K x 18 Pipelined Burst Synchronous SRAM with 2.5V I/O
* JTAG SA Version is not available with 100-pin TQFP package
4876 drw 13

Package Information
100-Pin Thin Quad Plastic Flatpack TQFP 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Information available on the IDT website

IDT71V2576, IDT71V2578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Commercial and Industrial Temperature Ranges

Datasheet Document History
7/23/99 9/17/99
12/31/99

Pg. 8 Pg. 11 Pg. 18 Pg. 20 Pg. 1, 8, 11, 19
04/04/00

Pg. 1, 4, 8, 11, 19 Pg. 18 Pg. 4
06/01/00 07/15/00
10/25/00 04/22/03 06/30/03

Pg. 20 Pg. 7 Pg. 8 Pg. 20

Pg. 8 Pg. 4 Pg. 1,2,3,5-9 Pg. 5-8

Pg. 19,20 Pg. 21-23 Pg. 24
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
for Tech Support 800-345-7015

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V2576S150PFI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V2576S150PFI8 637333