IDT5V9910A-2SOG

IDT5V9910A-2SOG Datasheet

IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

Part	Datasheet
IDT5V9910A-2SOG	IDT5V9910A-2SOG (pdf)

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PDF Datasheet Preview
IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. IDT5V9910A FEATURES: • Eight zero delay outputs • <250ps of output to output skew • Selectable positive or negative edge synchronization • Synchronous output enable • Output frequency 15MHz to 85MHz • 3 skew grades: IDT5V9910A-2 tSKEW0<250ps IDT5V9910A-5 tSKEW0<500ps IDT5V9910A-7 tSKEW0<750ps • 3-level inputs for PLL range control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter <200ps peak-to-peak • Available in SOIC package DESCRIPTION: The IDT5V9910A is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter or frequency variation while still providing accurate responses to input frequency changes. FUNCTIONAL BLOCK DIAGRAM VCCQ/PE GND/sOE FS Q6 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL c 2001 Integrated Device Technology, Inc. TEMPERATURE 1 RANGES SEPTEMBER 2001 DSC 5847/1 IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. PIN CONFIGURATION REF 1 VCCQ V C Q /P E VCCN GND 9 Q2 10 Q3 11 VCCN 24 GND 23 TEST 22 NC 21 GND/sOE 20 VCCN 19 Q7 18 Q6 17 GND 16 Q5 15 Q4 14 VCCN 13 FB SOIC TOP VIEW COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage to Ground Unit to +7 V ORDERING INFORMATION Device Type Package Process COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Blank I Commercial 0°C to +70°C Industrial -40°C to +85°C Small Outline IC 300-mil 5V9910A-2 3.3V Low Skew PLL Clock Driver TurboClock Jr. 5V9910A-5 5V9910A-7 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 for Tech Support 408 654-6459

PDF Datasheet Preview

IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

IDT5V9910A

FEATURES:
• Eight zero delay outputs
• <250ps of output to output skew
• Selectable positive or negative edge synchronization
• Synchronous output enable
• Output frequency 15MHz to 85MHz
• 3 skew grades:

IDT5V9910A-2 tSKEW0<250ps IDT5V9910A-5 tSKEW0<500ps IDT5V9910A-7 tSKEW0<750ps
• 3-level inputs for PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter <200ps peak-to-peak
• Available in SOIC package

DESCRIPTION:

The IDT5V9910A is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs.

When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except Q2 and Q3 are synchronously disabled.

Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF.

The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly.

An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter or frequency variation while still providing accurate responses to input frequency changes.

FUNCTIONAL BLOCK DIAGRAM

VCCQ/PE

GND/sOE

FS Q6

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL
c 2001 Integrated Device Technology, Inc.

TEMPERATURE 1

RANGES

SEPTEMBER 2001

DSC 5847/1

IDT5V9910A 3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

PIN CONFIGURATION

REF 1

VCCQ

V C Q /P E

VCCN

GND 9

Q2 10

Q3 11

VCCN
24 GND 23 TEST 22 NC 21 GND/sOE 20 VCCN 19 Q7 18 Q6 17 GND 16 Q5 15 Q4 14 VCCN 13 FB

SOIC TOP VIEW

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS 1

Supply Voltage to Ground

Unit
to +7 V
ORDERING INFORMATION

Device Type Package Process

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Blank I

Commercial 0°C to +70°C Industrial -40°C to +85°C

Small Outline IC 300-mil
5V9910A-2 3.3V Low Skew PLL Clock Driver TurboClock Jr. 5V9910A-5 5V9910A-7

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674
for Tech Support 408 654-6459

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT5V9910A-2SOG Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT5V9910A-2SOG 637302