MC100ES6030EG

MC100ES6030EG Datasheet

Order Number MC100ES6030 Rev 0, 10/2003

Part	Datasheet
MC100ES6030EG	MC100ES6030EG (pdf)

PDF Datasheet Preview
Freescale Semiconductor, Inc... MOTOROLA SEMICONDUCTOR TECHNFIrCeAeLsDcAaTAle Semiconductor, Inc. Preliminary Information 2.52/3.5.3/V3E.3CVL TEriCplLe DTFrliipp-lFeloDp wFilthip- Flop Sewt aintdhRSeesett and Reset DATA SHEET MC100ESM6C010300ES6030 The MC100ES6030 is a triple master--slave D flip--flop with differential outputs. When the clock input is low, data enters the master latch and transfers to the slave during a positive transition on the clock input. Each flip--flop has individual Reset inputs while the Set input is shared. The Set and Reset inputs are asynchronous and override the clock inputs. • GHz minimum toggle frequency • 450 ps typical propagation delay • LVPECL operating range VCC = V to V, VEE = 0 V • LVECL operating range VCC = 0 V, VEE = V to V • 20--lead SOIC package • Ambient temperature range --40°C to +85°C DW SUFFIX 20--LEAD SOIC PACKAGE CASE 751D ORDERING INFORMATION Device MC100ES6030DW Package SO--20 MC100ES6030DWR2 SO--20 VCC Q0 20 19 18 VCC Q1 VCC Q2 Q2 VEE 12 11 S012 D0 CLK0 R0 D1 CLK1 R1 D2 CLK2 R2 Figure 20--Lead Pinout Top View and Logic Diagram PIN DESCRIPTION PIN D0--D2 R0--R2 CLK0--CLK2 S012 Q0--Q2, Q0--Q2 VCC VEE FUNCTION ECL Data Inputs ECL Reset Inputs ECL Clock Inputs ECL Common Set Input ECL Differential Data Outputs Positive Supply Negative Supply TRUTH TABLE CLK Q X Undef Z = LOW to HIGH Transition X = Don’t Care This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Iuncct, MC100ES6030 Freescale Semiconductor, Inc... MC100ES6030 2.5/3.3V ECL Triple D Flip-Flop with Set and Reset MC100ES6030 Freescale Semiconductor, Inc. NETCOM Table GENERAL SPECIFICATIONS Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Thermal Resistance Junction--to--Ambient 0 LFPM, 20 SOIC 500 LFPM, 20 SOIC Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Value Table ABSOLUTE MAXIMUM RATINGSa Rating

PDF Datasheet Preview

Freescale Semiconductor, Inc...

MOTOROLA

SEMICONDUCTOR

TECHNFIrCeAeLsDcAaTAle

Semiconductor,

Inc.

Preliminary Information 2.52/3.5.3/V3E.3CVL TEriCplLe DTFrliipp-lFeloDp wFilthip- Flop Sewt aintdhRSeesett and Reset

DATA SHEET

MC100ESM6C010300ES6030

The MC100ES6030 is a triple master--slave D flip--flop with differential outputs. When the clock input is low, data enters the master latch and transfers to the slave during a positive transition on the clock input.

Each flip--flop has individual Reset inputs while the Set input is shared. The Set and Reset inputs are asynchronous and override the clock inputs.
• GHz minimum toggle frequency
• 450 ps typical propagation delay
• LVPECL operating range VCC = V to V, VEE = 0 V
• LVECL operating range VCC = 0 V, VEE = V to V
• 20--lead SOIC package
• Ambient temperature range --40°C to +85°C

DW SUFFIX 20--LEAD SOIC PACKAGE

CASE 751D
ORDERING INFORMATION

Device MC100ES6030DW

Package SO--20

MC100ES6030DWR2

SO--20

VCC Q0 20 19 18

VCC Q1 VCC Q2

Q2 VEE 12 11

S012 D0 CLK0 R0

D1 CLK1 R1

D2 CLK2 R2

Figure 20--Lead Pinout Top View and Logic Diagram

PIN DESCRIPTION

PIN D0--D2 R0--R2 CLK0--CLK2 S012 Q0--Q2, Q0--Q2 VCC VEE

FUNCTION ECL Data Inputs ECL Reset Inputs ECL Clock Inputs ECL Common Set Input ECL Differential Data Outputs Positive Supply Negative Supply

TRUTH TABLE

CLK Q

X Undef

Z = LOW to HIGH Transition X = Don’t Care

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Iuncct,

MC100ES6030

Freescale Semiconductor, Inc...

MC100ES6030
2.5/3.3V ECL Triple D Flip-Flop with Set and Reset

MC100ES6030

Freescale Semiconductor, Inc.

NETCOM

Table GENERAL SPECIFICATIONS

Characteristics

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model Machine Model

Charged Device Model

Thermal Resistance Junction--to--Ambient
0 LFPM, 20 SOIC 500 LFPM, 20 SOIC

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Value

Table ABSOLUTE MAXIMUM RATINGSa

Rating

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Datasheet ID: MC100ES6030EG 637424