5T2110BBGI

5T2110BBGI Datasheet

IDT5T2110 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK

Part	Datasheet
5T2110BBGI	5T2110BBGI (pdf)

Related Parts	Information
5T2110BBGI8	5T2110BBGI8
5T2110NLGI	5T2110NLGI
5T2110NLGI8	5T2110NLGI8

PDF Datasheet Preview
IDT5T2110 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK INDUSTRIAL TEMPERATURE RANGE 2.5V ZERO DELAY PLL DIFFERENTIAL IDT5T2110 CLOCK DRIVER TERACLOCK PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015 FEATURES: • VDD • 6 differential outputs • Low skew 100ps all outputs • Selectable positive or negative edge synchronization • Tolerant of spread spectrum input clock • Synchronous output enable • Selectable inputs • Input frequency 4.17MHz to 250MHz • Output frequency 12.5MHz to 250MHz • 1.8V / 2.5V LVTTL up to 250MHz • HSTL / eHSTL up to 250MHz • Hot insertable and over-voltage tolerant inputs • 3-level inputs for selectable interface • 3-level inputs for feedback divide selection with multiply ratios of 1-6, 8, 10, 12 • Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input interface • Selectable differential or single-ended inputs and six differen- tial outputs • PLL bypass for DC testing • External differential feedback, internal loop filter • Low Jitter <75ps cycle-to-cycle • Power-down mode • Lock indicator • Available in BGA and VFQFPN package FUNCTIONAL BLOCK DIAGRAM DESCRIPTION: The IDT5T2110 is a 2.5V PLL differential clock driver intended for high performance computing and data-communications applications. The IDT5T2110 has six differential outputs in six banks, including a dedicated differential feedback. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The feedback bank allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication 1 to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality of 2 or The 5T2110 features a user-selectable, single-ended or differential input to six differential outputs. The differential clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The differential outputs can be synchronously enabled/disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF. OMODE FB/ VREF2 REF0/ VREF0 REF1/ VREF1 /N 33 DS1:0 1 REF_SEL PD PE FS LOCK PLL PLL_EN The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 c 2014 Integrated Device Technology, Inc. 1sOE Divide Select 1F2:1 2sOE Divide Select 2F2:1 3sOE Divide Select 3F2:1 4sOE Divide Select 4F2:1 Divide Select 5sOE 5F2:1 Divide Select FBF2:1 ORDERING INFORMATION Device Type Package INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C Industrial BB BBG NL Plastic Ball Grid Array PBGA - Green Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package VFQFPN - Green 5T2110 2.5V Zero Delay PLL Differential Clock Driver Teraclock 3/18/14 Product Discontinuation Notice - Last time buy expires January 27, 2015, PDN# CQ-14-01 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT5T2110 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK

INDUSTRIAL TEMPERATURE RANGE
2.5V ZERO DELAY PLL DIFFERENTIAL IDT5T2110 CLOCK DRIVER TERACLOCK

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015

FEATURES:
• VDD
• 6 differential outputs
• Low skew 100ps all outputs
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
• Input frequency 4.17MHz to 250MHz
• Output frequency 12.5MHz to 250MHz
• 1.8V / 2.5V LVTTL up to 250MHz
• HSTL / eHSTL up to 250MHz
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• 3-level inputs for feedback divide selection with multiply ratios
of 1-6, 8, 10, 12
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and six differen-
tial outputs
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter <75ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Available in BGA and VFQFPN package

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION:

The IDT5T2110 is a 2.5V PLL differential clock driver intended for high performance computing and data-communications applications. The IDT5T2110 has six differential outputs in six banks, including a dedicated differential feedback. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent.

The feedback bank allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication 1 to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality of 2 or

The 5T2110 features a user-selectable, single-ended or differential input to six differential outputs. The differential clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The differential outputs can be synchronously enabled/disabled.

Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF.

OMODE

FB/ VREF2

REF0/ VREF0

REF1/ VREF1
/N 33 DS1:0
1 REF_SEL

PD PE FS LOCK PLL

PLL_EN

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE 1
c 2014 Integrated Device Technology, Inc.
1sOE

Divide Select
1F2:1
2sOE

Divide Select
2F2:1 3sOE

Divide Select
3F2:1 4sOE

Divide Select
4F2:1

Divide Select
5sOE
5F2:1

Divide Select

FBF2:1
ORDERING INFORMATION

Device Type Package

INDUSTRIAL TEMPERATURE RANGE
-40°C to +85°C Industrial

BB BBG NL

Plastic Ball Grid Array PBGA - Green Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package VFQFPN - Green
5T2110 2.5V Zero Delay PLL Differential Clock Driver Teraclock
3/18/14

Product Discontinuation Notice - Last time buy expires January 27, 2015, PDN# CQ-14-01

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5T2110BBGI Datasheet file may be downloaded here without warranties.

Datasheet ID: 5T2110BBGI 637272