954119DFLFT

954119DFLFT Datasheet

ICS954119 Advance Information

Part	Datasheet
954119DFLFT	954119DFLFT (pdf)

Related Parts	Information
954119DFLF	954119DFLF

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Integrated Circuit Systems, Inc. ICS954119 Advance Information Programmable Timing Control Hub for Next Gen P4 processor Recommended Application CK410 compliant clock Output Features • 2 - 0.7V current-mode differential CPU pairs • 1 - 0.7V current-mode differential SRC pair • 6 - PCI 33MHz • 3 - PCICLK_F, 33MHz free-running • 1 - USB, 48MHz • 1 - 24/48 MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 2 - REF, 14.318MHz • 5 - PCI-Express 0.7V current differential pairs Key Specifications • CPU/SRC outputs cycle-cycle jitter < 85ps • PCI outputs cycle-cycle jitter < 250ps • +/- 300ppm frequency accuracy on CPU & SRC clocks Features/Benefits • Programmable output frequencies • Programmable output skew. • Programmable spread percentage for EMI control. • Programmable watch dog safe frequency. • Supports tight ppm accuracy clocks for Serial-ATA • Supports spread spectrum modulation, 0 to down spread, center spread, and center spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Supports undriven differential CPU, SRC pair in PD# for power management. Functionality Bit4 Bit3 Bit2 Bit1 Bit0 CPU PCIEX SRC FSLC FSLB FSLA MHz PCI MHz Pin Configuration GND 1 56 VDDPCI PCICLK3 2 55 PCICLK2 PCICLK4 3 54 PCICLK1 PCICLK5 4 53 PCICLK0 GND 5 VDDPCI 6 PCICLK_F0 7 52 Reset# 51 REF0/FSLC 50 REF1 FSLA/PCICLK_F1 8 FSLB/PCICLK_F2 9 VDD48 10 49 GND 48 X1 47 X2 **SEL24_48#/24_48MHz 11 46 VDDREF ICS954119 USB_48MHz 12 45 SCLK GND 13 44 SDATA DOTT_ 96MHz 14 43 CPUCLKT0 DOTC_96MHz 15 42 CPUCLKC0 Vtt_PwrGd#/PD 16 41 VDDCPU PCIEXT0 17 40 CPUCLKT1 Ordering Information ICS954119yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free Optional Package Type F = SSOP Prefix ICS = Standard Device

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICS954119 Advance Information

Programmable Timing Control Hub for Next Gen P4 processor

Recommended Application CK410 compliant clock

Output Features
• 2 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 6 - PCI 33MHz
• 3 - PCICLK_F, 33MHz free-running
• 1 - USB, 48MHz
• 1 - 24/48 MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 2 - REF, 14.318MHz
• 5 - PCI-Express 0.7V current differential pairs Key Specifications
• CPU/SRC outputs cycle-cycle jitter < 85ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks

Features/Benefits
• Programmable output frequencies
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Programmable watch dog safe frequency.
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to
down spread, center spread, and center spread
• Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD# for power management.

Functionality

Bit4 Bit3 Bit2 Bit1 Bit0 CPU PCIEX SRC FSLC FSLB FSLA MHz

PCI MHz

Pin Configuration

GND 1
56 VDDPCI

PCICLK3 2
55 PCICLK2

PCICLK4 3
54 PCICLK1

PCICLK5 4
53 PCICLK0

GND 5 VDDPCI 6 PCICLK_F0 7
52 Reset# 51 REF0/FSLC 50 REF1

FSLA/PCICLK_F1 8 FSLB/PCICLK_F2 9

VDD48 10
49 GND 48 X1 47 X2
**SEL24_48#/24_48MHz 11
46 VDDREF

ICS954119

USB_48MHz 12
45 SCLK

GND 13
44 SDATA

DOTT_ 96MHz 14
43 CPUCLKT0

DOTC_96MHz 15
42 CPUCLKC0

Vtt_PwrGd#/PD 16
41 VDDCPU

PCIEXT0 17
40 CPUCLKT1
Ordering Information

ICS954119yFLF-T

Example:

ICS XXXX y F LF- T

Designation for tape and reel packaging

Lead Free Optional

Package Type F = SSOP

Prefix ICS = Standard Device

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Datasheet ID: 954119DFLFT 637221