ICS9179BF-01T

ICS9179BF-01T Datasheet

ICS9179 B -01

Part	Datasheet
ICS9179BF-01T	ICS9179BF-01T (pdf)

Related Parts	Information
ICS9179BF-01	ICS9179BF-01
9179BF-01LF	9179BF-01LF
9179BF-01LFT	9179BF-01LFT

PDF Datasheet Preview
Integrated Circuit Systems, Inc. ICS9179 B -01 Low Skew Buffers The ICS9179B-01 generates SDRAM clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Pentium II. An output enable is provided for testability. The device is a buffer with low output to output skew. This is a Fanout buffer device, not using an internal PLL. This buffer can also be a feedback to an external PLL stage for phase synchronization to a master clock. The individual clock outputs are addressable through I2C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed. • High speed, low noise non-inverting 0:17 buffer for SDRAM clock buffer applications. • Supports up to four SDRAM DIMMS • Synchronous clocks skew matched to 250 ps window on SDRAM. • I2C Serial Configuration interface to allow individual clocks to be stopped. • Multiple VDD, VSS pins for noise reduction • Tri-state pin for testing • Custom configurations available • 3.0V 3.7V supply range • 48-pin SSOP package Block Diagram Pin Configuration 48-Pin SSOP PentiumPro is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ICS9179 B -01 Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 4, 5, 8, 9 SDRAM 0:3 OUT SDRAM Byte 0 clock outputs1 13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45 21, 28 11 24 25 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 23 26 1, 2, 47, 48 SDRAM 4:7 SDRAM 8:11 SDRAM 12:15 SDRAM 16:17 BUF_IN OE SDATA SCLK VDDS GNDS I/O I/O SDRAM Byte 1 clock outputs1 SDRAM Byte 2 clock outputs1 SDRAM Byte 3 clock outputs1 SDRAM clock outputs useable for feedback.1 Input for buffers Tri-states all outputs when held LOW. Has internal pull-up.2 Data pin for I2C circuitry3 Clock pin for I2C circuitry3 PWR 3.3V Power supply for SDRAM buffer PWR Ground for SDRAM buffer PWR 3.3V Power supply for I2C circuitry PWR Ground for I2C circuitry - Pins are not internally connected At power up all eighteen SDRAM outputs are enabled and active. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for complete platform flexibility. Power Groups Ordering Information 9179BF-01LF Example: XXXX F - PPP denotes Pb-free configuration, RoHS compliant Pattern Number 2 or 3 digit number for parts with ROM code patterns Package Type F=SSOP Device Type ICS9179 B -01

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICS9179 B -01

Low Skew Buffers

The ICS9179B-01 generates SDRAM clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Pentium II. An output enable is provided for testability.

The device is a buffer with low output to output skew. This is a Fanout buffer device, not using an internal PLL. This buffer can also be a feedback to an external PLL stage for phase synchronization to a master clock.

The individual clock outputs are addressable through I2C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed.
• High speed, low noise non-inverting 0:17 buffer for

SDRAM clock buffer applications.
• Supports up to four SDRAM DIMMS
• Synchronous clocks skew matched to 250 ps
window on SDRAM.
• I2C Serial Configuration interface to allow individual
clocks to be stopped.
• Multiple VDD, VSS pins for noise reduction
• Tri-state pin for testing
• Custom configurations available
• 3.0V 3.7V supply range
• 48-pin SSOP package

Block Diagram

Pin Configuration
48-Pin SSOP

PentiumPro is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

ICS9179 B -01

Pin Descriptions

PIN NUMBER PIN NAME TYPE DESCRIPTION
4, 5, 8, 9

SDRAM 0:3 OUT SDRAM Byte 0 clock outputs1
13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45
21, 28 11
24 25 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 23 26 1, 2, 47, 48

SDRAM 4:7 SDRAM 8:11 SDRAM 12:15 SDRAM 16:17

BUF_IN OE

SDATA SCLK

VDDS GNDS

I/O I/O

SDRAM Byte 1 clock outputs1 SDRAM Byte 2 clock outputs1 SDRAM Byte 3 clock outputs1 SDRAM clock outputs useable for feedback.1 Input for buffers Tri-states all outputs when held LOW. Has internal pull-up.2 Data pin for I2C circuitry3 Clock pin for I2C circuitry3

PWR 3.3V Power supply for SDRAM buffer

PWR Ground for SDRAM buffer

PWR 3.3V Power supply for I2C circuitry PWR Ground for I2C circuitry
- Pins are not internally connected

At power up all eighteen SDRAM outputs are enabled and active.

OE has a 100K Ohm internal pull-up resistor to keep all outputs active.

The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for complete platform flexibility.

Power Groups
Ordering Information
9179BF-01LF

Example:

XXXX F - PPP
denotes Pb-free configuration, RoHS compliant

Pattern Number 2 or 3 digit number for parts with ROM code patterns

Package Type F=SSOP

Device Type

ICS9179 B -01

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Datasheet ID: ICS9179BF-01T 637213