ICS8725AY-01LF

ICS8725AY-01LF Datasheet

ICS8725-01

Part	Datasheet
ICS8725AY-01LF	ICS8725AY-01LF (pdf)

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Integrated Circuit Systems, Inc. ICS8725-01 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR The ICS8725-01 is a highly versatile 1:5 Dif- ferential-to-HSTL clock generator and a HiPerClockS member of the HiPerClockS family of High Performance Clock Solutions from ICS. The ICS8725-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and out- put divider are each programmable, thereby allowing for the following output-to-input frequency ratios 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • Five differential HSTL outputs • Selectable differential CLKx, nCLKx input pairs • CLKx, nCLKx pairs can accept the following differential input levels LVPECL, LVDS, HSTL, SSTL, HCSL • Output frequency range 31.25MHz to 700MHz • Input frequency range 31.25MHz to 700MHz • VCO range 250MHz to 700MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Programmable dividers allow for the following output-to-input frequency ratios 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • Static phase offset ±100ps • Cycle-to-cycle jitter 25ps • Output skew 25ps • 3.3V core, 1.8V output operating supply • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT PLL_SEL CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN SEL0 SEL1 SEL2 SEL3 8725AY-01 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Q0 nQ0 Q1 nQ1 32 31 30 29 28 27 26 25 Q2 nQ2 SEL0 1 TABLE ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8725AY-01 ICS8725AY-01 32 Lead LQFP tray 0°C to 70°C ICS8725AY-01T ICS8725AY-01 32 Lead LQFP 1000 tape & reel 0°C to 70°C ICS8725AY-01LF ICS8725AY01L 32 Lead "Lead-Free" LQFP tray 0°C to 70°C ICS8725AY-01LFT ICS8725AY01L 32 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated ICS assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8725AY-01 Integrated Circuit Systems, Inc. ICS8725-01 1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR B T10 Page 1 5 3 5 2 8 2 4 7 8 1 15 8 11-12 Description of Change Updated Output Rise/Fall Time Diagram. Format changes. Changed LVHSTL to HSTL throughout data sheet to conform with JEDEC terminology. Added Power Supply Filtering Techniques section. Added Differential Input Interface section. Updated format throughout data sheet. HSTL table - changed VOX minimum to 40% and maximum to 60% added NOTE Features Section - add Lead-Free bullet. Ordering Information Table - added Lead-Free package and note. Added Recommendations for Unused Input and Output Pins. Corrected Power Considerations, Power Dissipation calculation. Date 11/2/01 11/20/01 8/22/02 9/26/03 11/11/04 6/9/05 11/15/05 8725AY-01

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICS8725-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR

The ICS8725-01 is a highly versatile 1:5 Dif-
ferential-to-HSTL clock generator and a

HiPerClockS member of the HiPerClockS family of High

Performance Clock Solutions from ICS. The

ICS8725-01 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to
700MHz. The reference divider, feedback divider and out-
put divider are each programmable, thereby allowing for
the following output-to-input frequency ratios 8:1, 4:1, 2:1,
1:1, 1:2, 1:4, The external feedback allows the device
to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the

PLL for system test and debug purposes. In bypass mode,
the reference clock is routed around the PLL and into the
internal output dividers.
• Five differential HSTL outputs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels LVPECL, LVDS, HSTL, SSTL, HCSL
• Output frequency range 31.25MHz to 700MHz
• Input frequency range 31.25MHz to 700MHz
• VCO range 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input frequency ratios 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Static phase offset ±100ps
• Cycle-to-cycle jitter 25ps
• Output skew 25ps
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages

BLOCK DIAGRAM

PIN ASSIGNMENT

PLL_SEL

CLK0 nCLK0

CLK1 nCLK1 CLK_SEL FB_IN nFB_IN

SEL0 SEL1 SEL2 SEL3
8725AY-01
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

Q0 nQ0

Q1 nQ1
32 31 30 29 28 27 26 25

Q2 nQ2

SEL0 1
TABLE ORDERING INFORMATION

Part/Order Number

Marking

Package

Shipping Packaging Temperature

ICS8725AY-01

ICS8725AY-01
32 Lead LQFP
tray
0°C to 70°C

ICS8725AY-01T

ICS8725AY-01
32 Lead LQFP
1000 tape & reel
0°C to 70°C

ICS8725AY-01LF

ICS8725AY01L
32 Lead "Lead-Free" LQFP
tray
0°C to 70°C

ICS8725AY-01LFT

ICS8725AY01L
32 Lead "Lead-Free" LQFP
1000 tape & reel
0°C to 70°C

NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated ICS assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
8725AY-01

Integrated Circuit Systems, Inc.

ICS8725-01
1:5 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR

B T10

Page 1 5 3 5 2 8
2 4 7 8
1 15 8 11-12

Description of Change

Updated Output Rise/Fall Time Diagram.

Format changes. Changed LVHSTL to HSTL throughout data sheet to conform with JEDEC terminology.

Added Power Supply Filtering Techniques section.

Added Differential Input Interface section.
Updated format throughout data sheet. HSTL table - changed VOX minimum to 40% and maximum to 60% added NOTE Features Section - add Lead-Free bullet. Ordering Information Table - added Lead-Free package and note. Added Recommendations for Unused Input and Output Pins. Corrected Power Considerations, Power Dissipation calculation.

Date 11/2/01 11/20/01 8/22/02
9/26/03
11/11/04 6/9/05
11/15/05
8725AY-01

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS8725AY-01LF Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS8725AY-01LF 637189