GCIXP1240AB

GCIXP1240AB Datasheet

i GCIXP1240xx INTEL M C 2001

Part	Datasheet
GCIXP1240AB	GCIXP1240AB (pdf)

Related Parts	Information
GCIXP1240AA	GCIXP1240AA

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IXP1240 Network Processor Product Features Datasheet The IXP1240 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1240 are the performance of ASIC hardware along with programmability of a microprocessor. s Applications s Industry Standard 64-bit SDRAM Interface Multi-layer LAN Switches Peak bandwidth of up to 928 Mbytes/sec Multi-protocol Telecommunications Products Address up to 256 Mbytes of SDRAM Broadband Cable Products Memory bandwidth improvement through Remote Access Devices bank switching Intelligent PCI adapters Read-modify-write support s Integrated StrongARM Core High-performance, low-power, 32-bit Byte aligner/merger Cyclic Redundancy Check CRC Embedded RISC processor s Industry Standard 32-bit SRAM Interface 16 Kbyte instruction cache Peak bandwidth of up to 464 Mbytes/sec 8 Kbyte data cache Address up to 8 Mbytes of SRAM 512 byte mini-cache for data that is used once Up to 8 Mbytes FlashROM for booting and then discarded StrongARM Core Write buffer Supports atomic push/pop operations Memory management unit Supports atomic bit set and bit clear Access to IXP1240 FBI Unit, PCI Unit and operations SDRAM Unit via the ARM* AMBA Bus Memory bandwidth improvement by reduced s Six Integrated Programmable Microengines read/write turnaround bus cycles Operating frequency of up to 232 MHz Multi-thread support of four threads per microengine Single-cycle ALU and shift operations Zero context swap overhead Large Register Set 128 General-Purpose and 128 Transfer Registers 2 K x 32-bit Instruction Control Store Access to the IXP1240 FBI Unit, PCI DMA channels, SRAM, and SDRAM s Other Integrated Features Hardware Hash Unit for generation of 48- or 64-bit adaptive polynomial hash keys Serial UART port Real Time Clock Four general-purpose I/O pins Four 24-bit timers with CPU watchdog support Limited JTAG Support 4 Kbyte Scratchpad Memory Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Copyright Intel Corporation, 2001 Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others. Datasheet IXP1240 Network Processor Contents Product Description 9 Functional Conventions StrongARM Microengines FBI Unit and the IX IX Bus Access Behavior Reset and Idle Bus Considerations SDRAM and SRAM SDRAM Unit SDRAM Bus Access Behavior SDRAM Cyclic Redundancy Checking CRC SDRAM Configurations SRAM Types SRAM Configurations BootROM Configurations SRAM Bus Access Behavior PCI Unit PCI Arbitration and Central Function Support Device Reset Hardware Initiated Software Initiated Reset PCI Initiated Reset Watchdog Timer Initiated Reset Signal Description Pinout Pin Type Legend Pin Description, Grouped by Processor Support SRAM Interface Pins SDRAM Interface Pins IX Bus Interface General Purpose Serial Port UART Pins PCI Interface Pins Power Supply Pins IEEE Interface Pins Miscellaneous Test Pin Usage Summary Pin/Signal Signals Listed in Alphabetical Order IX Bus Pins Function Listed by Operating IX Bus Decode Table Listed by Operating Mode Type Pin State During Datasheet IXP1240 Network Processor Pullup/Pulldown and Unused Pin Guidelines 66 Electrical Specifications 67 Absolute Maximum Ratings 67 DC 70 Type 1 Driver DC Specifications 70 Type 2 Driver DC Specifications 71 Overshoot/Undershoot Specifications 71 AC Specifications 72 Clock Timing Specifications 72 PXTAL Clock 72 PXTAL Clock Oscillator 73 PCI 73 PCI Electrical Specification 73 PCI Clock Signal AC Parameter Measurements....................... 73 PCI Bus Signals 75 76 Reset Timings Specification 76 IEEE 77 IEEE Timing Specifications 78 IX 80 FCLK Signal AC Parameter 80 IX Bus Signals Timing 81 IX Bus 83 117 TK_IN/TK_OUT 120 SRAM Interface 120 SRAM SCLK Signal AC Parameter Measurements 120 SRAM Bus Signal Timing 122 SRAM Bus - SRAM Signal Protocol and Timing 124 SRAM Bus - BootROM and SlowPort Timings........................ 129 SRAM Bus - BootRom Signal Protocol and Timing................. 129 SRAM Bus - Slow-Port Device Signal Protocol and Timing 132 SDRAM Interface 136 SDCLK AC Parameter 136 SDRAM Bus Signal Timing 137 SDRAM Signal Protocol 138 Asynchronous Signal Timing 143 Mechanical 144 Package Dimensions 144 IXP1240 Package Dimensions mm 146 Figures 1 2 3 4 5 6 Block 9 System Block 10 SDRAM Unit Block Diagram 16 SRAM Unit Block Diagram 19 Reset Logic 24 Pinout Diagram 26 Datasheet IXP1240 Network Processor 64-Bit Bidirectional IX Bus, 1-2 MAC 64-Bit Bidirectional IX Bus, 1-2 MAC Mode, FastPort Device 64-Bit Bidirectional IX Bus, 3+ MAC 10 32-Bit Unidirectional IX Bus, 1-2 MAC Mode 11 32-bit Unidirectional IX Bus, 3+ MAC Mode 3-4 MACs Supported 12 Typical IXP1240 Heatsink 13 PXTAL Clock Input 14 PCI Clock Signal AC Parameter 15 PCI Bus Signals 16 RESET_IN_L Timing Diagram 17 IEEE 1149.1/Boundary-Scan General 18 IEEE 1149.1/Boundary-Scan Tri-State

PDF Datasheet Preview

IXP1240 Network Processor

Product Features

Datasheet

The IXP1240 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1240 are the performance of ASIC hardware along with programmability of a microprocessor.
s Applications
s Industry Standard 64-bit SDRAM Interface

Multi-layer LAN Switches

Peak bandwidth of up to 928 Mbytes/sec

Multi-protocol Telecommunications Products Address up to 256 Mbytes of SDRAM

Broadband Cable Products

Memory bandwidth improvement through

Remote Access Devices
bank switching

Intelligent PCI adapters

Read-modify-write support
s Integrated StrongARM Core High-performance, low-power, 32-bit

Byte aligner/merger Cyclic Redundancy Check CRC

Embedded RISC processor
s Industry Standard 32-bit SRAM Interface
16 Kbyte instruction cache

Peak bandwidth of up to 464 Mbytes/sec
8 Kbyte data cache

Address up to 8 Mbytes of SRAM
512 byte mini-cache for data that is used once Up to 8 Mbytes FlashROM for booting
and then discarded

StrongARM Core

Write buffer

Supports atomic push/pop operations

Memory management unit

Supports atomic bit set and bit clear

Access to IXP1240 FBI Unit, PCI Unit and
operations

SDRAM Unit via the ARM* AMBA Bus

Memory bandwidth improvement by reduced
s Six Integrated Programmable Microengines
read/write turnaround bus cycles

Operating frequency of up to 232 MHz Multi-thread support of four threads per
microengine Single-cycle ALU and shift operations Zero context swap overhead Large Register Set 128 General-Purpose and
128 Transfer Registers 2 K x 32-bit Instruction Control Store Access to the IXP1240 FBI Unit, PCI DMA
channels, SRAM, and SDRAM
s Other Integrated Features Hardware Hash Unit for generation of 48- or 64-bit adaptive polynomial hash keys Serial UART port Real Time Clock Four general-purpose I/O pins Four 24-bit timers with CPU watchdog support Limited JTAG Support 4 Kbyte Scratchpad Memory
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at

Copyright Intel Corporation, 2001 Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries *Other names and brands may be claimed as the property of others.

Datasheet

IXP1240 Network Processor

Contents

Product Description 9

Functional

Conventions StrongARM* Microengines FBI Unit and the IX

IX Bus Access Behavior Reset and Idle Bus Considerations

SDRAM and SRAM SDRAM Unit SDRAM Bus Access Behavior SDRAM Cyclic Redundancy Checking CRC SDRAM Configurations SRAM Types SRAM Configurations BootROM Configurations SRAM Bus Access Behavior

PCI Unit PCI Arbitration and Central Function Support

Device Reset Hardware Initiated Software Initiated Reset PCI Initiated Reset Watchdog Timer Initiated Reset

Signal Description

Pinout Pin Type Legend Pin Description, Grouped by

Processor Support SRAM Interface Pins SDRAM Interface Pins IX Bus Interface General Purpose Serial Port UART Pins PCI Interface Pins Power Supply Pins IEEE Interface Pins Miscellaneous Test Pin Usage Summary Pin/Signal Signals Listed in Alphabetical Order IX Bus Pins Function Listed by Operating IX Bus Decode Table Listed by Operating Mode Type Pin State During

Datasheet

IXP1240 Network Processor

Pullup/Pulldown and Unused Pin Guidelines 66

Electrical Specifications 67

Absolute Maximum Ratings 67 DC 70

Type 1 Driver DC Specifications 70 Type 2 Driver DC Specifications 71 Overshoot/Undershoot Specifications 71 AC Specifications 72 Clock Timing Specifications 72 PXTAL Clock 72 PXTAL Clock Oscillator 73 PCI 73

PCI Electrical Specification 73 PCI Clock Signal AC Parameter Measurements....................... 73 PCI Bus Signals 75 76 Reset Timings Specification 76 IEEE 77 IEEE Timing Specifications 78 IX 80 FCLK Signal AC Parameter 80 IX Bus Signals Timing 81 IX Bus 83 117 TK_IN/TK_OUT 120 SRAM Interface 120 SRAM SCLK Signal AC Parameter Measurements 120 SRAM Bus Signal Timing 122 SRAM Bus - SRAM Signal Protocol and Timing 124 SRAM Bus - BootROM and SlowPort Timings........................ 129 SRAM Bus - BootRom Signal Protocol and Timing................. 129 SRAM Bus - Slow-Port Device Signal Protocol and Timing 132 SDRAM Interface 136 SDCLK AC Parameter 136 SDRAM Bus Signal Timing 137 SDRAM Signal Protocol 138 Asynchronous Signal Timing 143

Mechanical 144

Package Dimensions 144 IXP1240 Package Dimensions mm 146

Figures
1 2 3 4 5 6

Block 9 System Block 10 SDRAM Unit Block Diagram 16 SRAM Unit Block Diagram 19 Reset Logic 24 Pinout Diagram 26

Datasheet

IXP1240 Network Processor
64-Bit Bidirectional IX Bus, 1-2 MAC
64-Bit Bidirectional IX Bus, 1-2 MAC Mode, FastPort Device
64-Bit Bidirectional IX Bus, 3+ MAC
10 32-Bit Unidirectional IX Bus, 1-2 MAC Mode
11 32-bit Unidirectional IX Bus, 3+ MAC Mode 3-4 MACs Supported
12 Typical IXP1240 Heatsink
13 PXTAL Clock Input
14 PCI Clock Signal AC Parameter
15 PCI Bus Signals
16 RESET_IN_L Timing Diagram
17 IEEE 1149.1/Boundary-Scan General
18 IEEE 1149.1/Boundary-Scan Tri-State

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Datasheet ID: GCIXP1240AB 638948