8702BYLF

8702BYLF Datasheet

ICS8702

Part	Datasheet
8702BYLF	8702BYLF (pdf)

Related Parts	Information
8702BYLFT	8702BYLFT

PDF Datasheet Preview
Integrated Circuit Systems, Inc. ICS8702 LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR The ICS8702 is a low skew, ÷1, ÷2 Differential-to- LVCMOS Clock Generator and a member of the HiPerClockS family of High Performance Clock Solutions from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS/LVTTL levels. True or inverting, single-ended to LVCMOS translation can be achieved with a resistor bias on the nCLK or CLK inputs, respectively. The effective fan- out can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, supports enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the enabling and disabling of all outputs simultaneously. The ICS8702 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and repeatability. • Twenty LVCMOS outputs, 7Ω typical output impedance • One differential clock input pair • CLK, nCLK supports the following input types LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency 250MHz • Translates any differential input signal LVPECL, LVHSTL, LVDS to LVCMOS levels without external bias networks • Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew 200ps maximum • Bank skew 150ps maximum • Part-to-part skew 650ps maximum • Multiple frequency skew 250ps maximum • 3.3V or mixed 3.3V input, 2.5V output operating supply modes • 0°C to 70°C ambient operating temperature • Other divide values available on request • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND CLK nCLK DIV_SELA DIV_SELB DIV_SELC DIV_SELD nMR/OE BANK_EN0 BANK_EN1 8702BY QA0:QA4 QB0:QB4 QC0:QC4 QD0:QD4 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4 48 47 46 45 44 43 42 41 40 39 38 37 TABLE ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8702BY ICS8702BY 48 Lead LQFP tray 0°C to 70°C 8702BYT ICS8702BY 48 Lead LQFP 1000 tape & reel 0°C to 70°C 8702BYLF ICS8702BYLF 48 Lead "Lead-Free" LQFP tray 0°C to 70°C 8702BYLFT ICS8702BYLF 48 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated ICS assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8702BY Integrated Circuit Systems, Inc. ICS8702 LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR 4D 4B Page 4 6 4 6 11 2 10 1 2 9 12 Description of Change Added Power Dissipation and Driver Termination notes. Updated Output Rise/Fall Time Diagram. Format changes. Features Section added Lead-Free bullet. Pin Characteristics Table - changed CIN 4pF max to 4pF typical. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking, and note. Updated datasheet layout. Date 8/2/01 11/28/01 8/21/02 1/17/06 8702BY

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICS8702

LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

The ICS8702 is a low skew, ÷1, ÷2 Differential-to-

LVCMOS Clock Generator and a member of the

HiPerClockS family of High Performance Clock

Solutions from ICS. The ICS8702 is designed to
translate any differential signal levels to

LVCMOS/LVTTL levels. True or inverting, single-ended to

LVCMOS translation can be achieved with a resistor bias
on the nCLK or CLK inputs, respectively. The effective fan-
out can be increased from 20 to 40 by utilizing the ability of
the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, supports enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the enabling and disabling of all outputs simultaneously.

The ICS8702 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and repeatability.
• Twenty LVCMOS outputs, 7Ω typical output impedance
• One differential clock input pair
• CLK, nCLK supports the following input types LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency 250MHz
• Translates any differential input signal LVPECL, LVHSTL, LVDS to LVCMOS levels without external bias networks
• Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input
• Bank enable logic allows unused banks to be disabled in reduced fanout applications
• Output skew 200ps maximum
• Bank skew 150ps maximum
• Part-to-part skew 650ps maximum
• Multiple frequency skew 250ps maximum
• 3.3V or mixed 3.3V input, 2.5V output operating supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• Available in both standard and lead-free RoHS compliant packages

BLOCK DIAGRAM

PIN ASSIGNMENT

GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND

CLK nCLK DIV_SELA

DIV_SELB

DIV_SELC

DIV_SELD nMR/OE

BANK_EN0 BANK_EN1
8702BY

QA0:QA4 QB0:QB4 QC0:QC4 QD0:QD4

QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4
48 47 46 45 44 43 42 41 40 39 38 37
TABLE ORDERING INFORMATION

Part/Order Number

Marking

Package

Shipping Packaging Temperature
8702BY

ICS8702BY
48 Lead LQFP
tray
0°C to 70°C
8702BYT

ICS8702BY
48 Lead LQFP
1000 tape & reel
0°C to 70°C
8702BYLF

ICS8702BYLF
48 Lead "Lead-Free" LQFP
tray
0°C to 70°C
8702BYLFT

ICS8702BYLF
48 Lead "Lead-Free" LQFP
1000 tape & reel
0°C to 70°C

NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated ICS assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
8702BY

Integrated Circuit Systems, Inc.

ICS8702

LOW SKEW, ÷1, ÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
4D 4B

Page 4 6 4 6 11 2 10
1 2 9 12

Description of Change

Added Power Dissipation and Driver Termination notes.

Updated Output Rise/Fall Time Diagram.

Format changes.

Features Section added Lead-Free bullet.

Pin Characteristics Table - changed CIN 4pF max to 4pF typical. Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking, and note.

Updated datasheet layout.

Date 8/2/01 11/28/01 8/21/02
1/17/06
8702BY

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 8702BYLF Datasheet file may be downloaded here without warranties.

Datasheet ID: 8702BYLF 637187