DAC1208D750HN-C18

DAC1208D750HN-C18 Datasheet

DAC1208D750

Part	Datasheet
DAC1208D750HN-C18	DAC1208D750HN-C18 (pdf)

Related Parts	Information
DAC1208D750HN-C1	DAC1208D750HN-C1

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DAC1208D750 Dual 12-bit DAC up to 750 Msps or interpolating with JESD204A interface The DAC1208D750 is a high-speed 12-bit dual channel Digital-to-Analog Converter DAC with selectable or interpolating filters optimized for multi-carrier WCDMA transmitters. Because of its digital on-chip modulation, the DAC1208D750 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface SPI with a 32-bit Numerically Controlled Oscillator NCO and the phase is controlled by a 16-bit register. The DAC1208D750 also includes a or clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current. The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1208D750 is 4 and its maximum serial data rate is Gbps. The Multiple Device Synchronization MDS guarantees a maximum skew of one output clock period between several DAC devices. MDS incorporates modes Master/slave and All slave mode. Dual 12-bit resolution 750 Msps maximum update rate Selectable or interpolation filters Input data rate up to Msps Very low noise cap free integrated PLL 32-bit programmable NCO frequency Four JESD204A serial input lanes V and V power supplies LVDS compatible clock inputs IMD3 80 dBc fs = Msps fo = 140 MHz ACPR 71 dBc 2 carriers WCDMA fs = Msps fo = MHz Typical W power dissipation at interpolation, PLL off and 740 Msps Power-down mode and Sleep modes Differential scalable output current from mA to 22 mA On-chip V reference External analog offset control 10-bit auxiliary DACs Internal digital offset control Inverse sin x / x function Integrated Device Technology DAC1208D750 or interpolating DAC with JESD204A Two’s complement or binary offset data Fully compatible SPI port format LMF = 421 or LMF = 211 support Industrial temperature range from C to +85 C Differential CML receiver with Integrated PLL can be bypassed embedded termination Synchronization of multiple DAC outputs Embedded complex modulator Wireless infrastructure LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication LMDS/MMDS, point-to-point Direct Digital Synthesis DDS Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment ATE Ordering information Table Ordering information Type number Package Name DAC1208D750HN HVQFN64 Version plastic thermal enhanced very thin quad flat package no leads SOT804-3 64 terminals body 9 mm DAC1208D750 4 IDT All rights reserved. 2 of 96 x xx x xxx Block diagram Integrated Device Technology DAC1208D750 4 SDO SDIO SCS_N SCLK SYNC_OUTP SYNC_OUTN VIN_P0 L0 VIN_N0 VIN_P1 L1 VIN_N1 VIN_P2 L2 VIN_N2 VIN_P3 L3 VIN_N3 SPI CONTROL REGISTERS DIGITAL LAYER PROCESSING JESD204A LANE PROC FIR 1 2x FIR 2 2x FIR 3 2x NCO 32-bit frequency setting 16-bit phase adjustment 10-BIT OFFSET CONTROL 10-BIT GAIN CONTROL x sin x AUX. DAC I DAC AUXAP AUXAN IOUTAP IOUTAN Table Ordering information Table Pin description Table Limiting values Table Thermal characteristics Table Characteristics Table Digital Layer Processing Latency Table Read or Write mode access description Table Number of bytes to be transferred Table SPI timing characteristics Table Interpolation filter coefficients Table Inversion filter coefficients Table DAC transfer function Table IO fs coarse adjustment Table IO fs fine adjustment Table Digital offset adjustment Table Auxiliary DAC transfer function Table Page 0 register allocation map Table COMMON register address 00h bit description Table TXCFG register address 01h bit description Table PLLCFG register address 02h bit description 41 Table FREQNCO_LSB register address 03h bit description Table FREQNCO_LISB register address 04h bit description Table FREQNCO_UISB register address 05h bit description Table FREQNCO_MSB register address 06h bit description Table PHINCO_LSB register address 07h bit description Table PHINCO_MSB register address 08h bit description Table DAC_A_CFG_1 register address 09h bit description Table DAC_A_CFG_2 register address 0Ah bit description Table DAC_A_CFG_3 register address 0Bh bit description Table DAC_B_CFG_1 register address 0Ch bit description Table DAC_B_CFG_2 register address 0Dh bit description Table DAC_B_CFG_3 register address 0Eh bit description Table DAC_CFG register address 0Fh bit description Table DAC_CURRENT_0 register address 11h bit description Table DAC_CURRENT_1 register address 12h bit description Table DAC_CURRENT_2 register address 13h bit description Table DAC_CURRENT_3 register address 14h bit description Table DAC_SEL_PH_FINE register address 15h bit description 44 Table PHASECORR_CNTRL0 register address 16h bit description 44 Table PHASECORR_CNTRL1 register address 17h bit description 44 Table DAC_A_AUX_MSB register address 1Ah bit description 44 Table DAC_A_AUX_LSB register address 1Bh bit description 44 Table DAC_B_AUX_MSB register address 1Ch bit description 44 Table DAC_B_AUX_LSB register address 1Dh bit description 45 Table DAC_B_AUX_LSB register address 1Dh bit description 45 Table Bias current control table 45 Table Page 1 register allocation map 46 Table MDS_MAIN register address 00h bit description 47 Table MDS_WIN_PERIOD_A register address 01h bit description 47 Table MDS_WIN_PERIOD_B register address 02h bit description 47 Table MDS_MISCCNTRL0 register address 03h bit description 48 Table MDS_MAN_ADJUSTDLY register address 04h bit description 48 Table MDS_AUTO_CYCLES register address 05h bit description 48 Table MDS_MISCCNTRL1 register address 06h bit description 48 Table MDS_ADJDELAY register address 08h bit description 49 Table MDS_STATUS0 register address 09h bit description 49 Table MDS_STATUS1 register address 0Ah bit description 50 Table PAGE_ADDRESS register address 1Fh bit description 50 Table Page 2 register allocation map 51 Table MAINCONTROL register address 00h bit description 52 Table JCLK_CNTRL register address 03h bit description 52 Table RST_EXT_FCLK register address 04h bit description 53 Table RST_EXT_DCLK register address 05h bit Ordering information 2 Block diagram 3 Pinning information 4 Pinning 4 Pin description 4 Limiting values. 6 Thermal characteristics 6 Characteristics 7 Application information. 11 General description 11 JESD204A receiver 12 Lane input 13 Sync and word align 13 Comma detection and word align 14 Descrambler 15 Inter-lane alignment 15 Single device operation 15 Multi-device operation 15 Master/slave mode 17 All slave mode 20 Frame assembly 21 Serial Peripheral Interface SPI 23 Protocol description 23 SPI timing description 24 Clock input 25 FIR filters 26 Quadrature modulator and Numerically Controlled Oscillator NCO 27 NCO in 32-bit 27 Low-power NCO 27 Minus_3dB 27 x / sin x 27 DAC transfer function 28 Full-scale current 29 Regulation 29 External regulation 29 Full-scale current adjustment 29 Digital offset correction 30 Analog output 31 Auxiliary DACs 32 Output configuration 33 Basic output configuration 33 DC interface to an Analog Quadrature Modulator AQM 34 AC interface to an Analog Quadrature Modulator AQM 36 Phase correction. 37 Power and grounding 37 Configuration interface 37 Register description 37 Detailed descriptions of registers 37 Page 0 allocation map description 38 Page 0 bit definition detailed description 40 Page 1 allocation map description 46 Page 1 bit definition detailed description 47 Page 2 allocation map description 51 Page 2 bit definition detailed description 52 Page 4 allocation map description 56 Page 4 bit definition detailed description 58 Page 5 allocation map description 68 Page 5 bit definition detailed description 70 Page 6 allocation map description 77 Page 6 bit definition detailed description 79 Page 7 allocation map description 83 Page 7 bit definition detailed description 85 Package outline. 89 Abbreviations 90 Contact information 91 Tables 92 Contents. 96 DAC1208D750 4 IDT All rights reserved. 96 of 96

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DAC1208D750

Dual 12-bit DAC up to 750 Msps or interpolating with JESD204A interface

The DAC1208D750 is a high-speed 12-bit dual channel Digital-to-Analog Converter DAC with selectable or interpolating filters optimized for multi-carrier WCDMA transmitters.

Because of its digital on-chip modulation, the DAC1208D750 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface SPI with a 32-bit Numerically Controlled Oscillator NCO and the phase is controlled by a 16-bit register.

The DAC1208D750 also includes a or clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current.

The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1208D750 is 4 and its maximum serial data rate is Gbps.

The Multiple Device Synchronization MDS guarantees a maximum skew of one output clock period between several DAC devices. MDS incorporates modes Master/slave and All slave mode.

Dual 12-bit resolution
750 Msps maximum update rate

Selectable or interpolation filters

Input data rate up to Msps Very low noise cap free integrated PLL
32-bit programmable NCO frequency Four JESD204A serial input lanes

V and V power supplies LVDS compatible clock inputs

IMD3 80 dBc fs = Msps fo = 140 MHz

ACPR 71 dBc 2 carriers WCDMA fs = Msps fo = MHz

Typical W power dissipation at interpolation, PLL off and 740 Msps

Power-down mode and Sleep modes

Differential scalable output current from mA to 22 mA

On-chip V reference

External analog offset control 10-bit auxiliary DACs

Internal digital offset control

Inverse sin x / x function

Integrated Device Technology

DAC1208D750
or interpolating DAC with JESD204A

Two’s complement or binary offset data Fully compatible SPI port
format

LMF = 421 or LMF = 211 support

Industrial temperature range from
C to +85 C

Differential CML receiver with

Integrated PLL can be bypassed
embedded termination

Synchronization of multiple DAC outputs Embedded complex modulator

Wireless infrastructure LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication LMDS/MMDS, point-to-point Direct Digital Synthesis DDS Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment ATE
Ordering information
Table Ordering information

Type number

Package

Name

DAC1208D750HN

HVQFN64

Version
plastic thermal enhanced very thin quad flat package no leads SOT804-3 64 terminals body 9 mm

DAC1208D750 4

IDT All rights reserved.
2 of 96
x xx x xxx

Block diagram

Integrated Device Technology

DAC1208D750 4

SDO SDIO SCS_N SCLK

SYNC_OUTP

SYNC_OUTN

VIN_P0 L0

VIN_N0

VIN_P1 L1

VIN_N1

VIN_P2 L2

VIN_N2

VIN_P3 L3

VIN_N3

SPI CONTROL REGISTERS

DIGITAL LAYER PROCESSING

JESD204A

LANE PROC

FIR 1 2x

FIR 2 2x

FIR 3 2x

NCO 32-bit frequency setting 16-bit phase adjustment
10-BIT OFFSET CONTROL
10-BIT GAIN CONTROL
x sin x

AUX. DAC

I DAC

AUXAP AUXAN

IOUTAP IOUTAN
Table Ordering information Table Pin description Table Limiting values Table Thermal characteristics Table Characteristics Table Digital Layer Processing Latency Table Read or Write mode access description Table Number of bytes to be transferred Table SPI timing characteristics Table Interpolation filter coefficients Table Inversion filter coefficients Table DAC transfer function Table IO fs coarse adjustment Table IO fs fine adjustment Table Digital offset adjustment Table Auxiliary DAC transfer function Table Page 0 register allocation map Table COMMON register address 00h bit
description Table TXCFG register address 01h bit description Table PLLCFG register address 02h bit description 41 Table FREQNCO_LSB register address 03h bit
description Table FREQNCO_LISB register address 04h bit
description Table FREQNCO_UISB register address 05h bit
description Table FREQNCO_MSB register address 06h bit
description Table PHINCO_LSB register address 07h bit
description Table PHINCO_MSB register address 08h bit
description Table DAC_A_CFG_1 register address 09h bit
description Table DAC_A_CFG_2 register address 0Ah bit
description Table DAC_A_CFG_3 register address 0Bh bit
description Table DAC_B_CFG_1 register address 0Ch bit
description Table DAC_B_CFG_2 register address 0Dh bit
description Table DAC_B_CFG_3 register address 0Eh bit
description Table DAC_CFG register address 0Fh bit
description Table DAC_CURRENT_0 register address 11h
bit description Table DAC_CURRENT_1 register address 12h bit
description Table DAC_CURRENT_2 register address 13h bit
description Table DAC_CURRENT_3 register address 14h bit
description Table DAC_SEL_PH_FINE register address 15h
bit description 44 Table PHASECORR_CNTRL0 register
address 16h bit description 44 Table PHASECORR_CNTRL1 register
address 17h bit description 44 Table DAC_A_AUX_MSB register address 1Ah bit
description 44 Table DAC_A_AUX_LSB register address 1Bh bit
description 44 Table DAC_B_AUX_MSB register address 1Ch bit
description 44 Table DAC_B_AUX_LSB register address 1Dh bit
description 45 Table DAC_B_AUX_LSB register address 1Dh bit
description 45 Table Bias current control table 45 Table Page 1 register allocation map 46 Table MDS_MAIN register address 00h bit
description 47 Table MDS_WIN_PERIOD_A register address 01h
bit description 47 Table MDS_WIN_PERIOD_B register address 02h
bit description 47 Table MDS_MISCCNTRL0 register address 03h
bit description 48 Table MDS_MAN_ADJUSTDLY register
address 04h bit description 48 Table MDS_AUTO_CYCLES register address 05h
bit description 48 Table MDS_MISCCNTRL1 register address 06h
bit description 48 Table MDS_ADJDELAY register address 08h bit
description 49 Table MDS_STATUS0 register address 09h bit
description 49 Table MDS_STATUS1 register address 0Ah bit
description 50 Table PAGE_ADDRESS register address 1Fh bit
description 50 Table Page 2 register allocation map 51 Table MAINCONTROL register address 00h bit
description 52 Table JCLK_CNTRL register address 03h bit
description 52 Table RST_EXT_FCLK register address 04h bit
description 53 Table RST_EXT_DCLK register address 05h bit
Ordering information 2

Block diagram 3

Pinning information 4

Pinning 4

Pin description 4

Limiting values. 6

Thermal characteristics 6

Characteristics 7

Application information. 11

General description 11 JESD204A receiver 12 Lane input 13 Sync and word align 13 Comma detection and word align 14 Descrambler 15 Inter-lane alignment 15 Single device operation 15 Multi-device operation 15 Master/slave mode 17 All slave mode 20 Frame assembly 21 Serial Peripheral Interface SPI 23 Protocol description 23 SPI timing description 24 Clock input 25 FIR filters 26 Quadrature modulator and Numerically Controlled Oscillator NCO 27 NCO in 32-bit 27 Low-power NCO 27 Minus_3dB 27 x / sin x 27 DAC transfer function 28 Full-scale current 29 Regulation 29 External regulation 29 Full-scale current adjustment 29 Digital offset correction 30 Analog output 31 Auxiliary DACs 32 Output configuration 33 Basic output configuration 33 DC interface to an Analog Quadrature Modulator AQM 34 AC interface to an Analog Quadrature Modulator AQM 36 Phase correction. 37 Power and grounding 37 Configuration interface 37 Register description 37 Detailed descriptions of registers 37

Page 0 allocation map description 38 Page 0 bit definition detailed description 40 Page 1 allocation map description 46 Page 1 bit definition detailed description 47 Page 2 allocation map description 51 Page 2 bit definition detailed description 52 Page 4 allocation map description 56 Page 4 bit definition detailed description 58 Page 5 allocation map description 68 Page 5 bit definition detailed description 70 Page 6 allocation map description 77 Page 6 bit definition detailed description 79 Page 7 allocation map description 83 Page 7 bit definition detailed description 85

Package outline. 89

Abbreviations 90

Contact information 91

Tables 92

Contents. 96

DAC1208D750 4

IDT All rights reserved.
96 of 96

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Datasheet ID: DAC1208D750HN-C18 636939