DAC1005D750HW/C1:5

DAC1005D750HW/C1:5 Datasheet

DAC1005D750

Part	Datasheet
DAC1005D750HW/C1:5	DAC1005D750HW/C1:5 (pdf)

Related Parts	Information
DAC1005D750HW/C1,5	DAC1005D750HW/C1,5

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DAC1005D750 Dual 10-bit DAC, up to 750 Msps 4x and 8x interpolating The DAC1005D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter DAC with selectable or interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1005D750 allows the complex I and Q inputs to be converted from BaseBand BB to IF. The mixing frequency is adjusted via a Serial Peripheral Interface SPI with a 32-bit Numerically Controlled Oscillator NCO and the phase is controlled by a 16-bit register. Two modes of operation are available separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. A and clock multiplier enables the DAC1005D750 to provide the appropriate internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use of an external high frequency clock. The voltage regulator enables adjustment of the output full-scale current. Dual 10-bit resolution IMD3 74 dBc fs = Msps; 750 Msps maximum update rate fo = 140 MHz ACPR 64 dBc 2-carrier WCDMA; fs = Msps fo = MHz Selectable or interpolation filters Typical W power dissipation at interpolation, PLL off and 740 Msps Input data rate up to 185 Msps Power-down and Sleep modes Very low noise cap-free integrated PLL Differential scalable output current from mA to 22 mA 32-bit programmable NCO frequency On-chip V reference Dual port or Interleaved data modes External analog offset control 10-bit auxiliary DACs V and V power supplies Internal digital offset control LVDS compatible clock Inverse x / sin x function Two’s complement or binary offset Fully compatible SPI port data format V/3.3 V CMOS input data buffers Industrial temperature range from C to +85 C Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps 4x and 8x interpolating Wireless infrastructure LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication LMDS/MMDS, point-to-point Direct Digital Synthesis DDS Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment ATE Ordering information Table Ordering information Type number Package Name DAC1005D750HW HTQFP100 plastic thermal enhanced thin quad flat package 100 leads body 14 1 mm exposed die pad Version SOT638-1 DAC1005D750 5 IDT All rights reserved. 2 of 43 x xx x xxx Block diagram Integrated Device Technology DAC1005D750 5 DAC1005D750 Dual 10-bit DAC, up to 750 Msps 4x and 8x interpolating SCS_N SDIO SCLK 62 63 65 64 SPI DAC1005D750 I0 to I9 18 to 25, 28, 29 LATCH I FIR1 2x FIR2 2x FIR3 2x dual port/ interleaved data modes Q0 to Q9 41, 42, 45 to 48, 51 to 54 8 CLKP 9 CLKN LATCH Q FIR1 2x FIR2 2x FIR3 2x CLOCK GENERATOR/PLL Fig Block diagram RESET_N SYNCP 13 SYNCN Ordering information 2 Block diagram 3 Pinning information 4 Pinning 4 Pin description 5 Limiting values. 8 Thermal characteristics 8 Characteristics 9 Application information. 14 General description 14 Serial peripheral interface. 14 Protocol description 14 SPI timing description 15 Detailed descriptions of registers 17 Detailed register descriptions 19 Recommended configuration 24 Input data 24 Dual-port mode 24 Interleaved mode 25 Input clock 26 Timing 26 Timing when using the internal PLL on 27 Timing when using an external PLL off 27 FIR filters 27 Quadrature modulator and Numerically Controlled Oscillator NCO 28 NCO in 32-bit 29 Low-power NCO 29 Minus_3dB function 29 x / sin x 29 DAC transfer function. 30 Full-scale current 30 Regulation 30 Full-scale current adjustment. 31 Digital offset adjustment. 32 Analog output. 33 Auxiliary DACs 34 Output configuration. 34 Basic output configuration 34 DC interface to an Analog Quadrature Modulator AQM 35 AC interface to an Analog Quadrature Modulator AQM 37 Power and grounding. 38 Package outline. 39 Abbreviations 40 Glossary. 41 Contact information 42 Contents. 43 DAC1005D750 5 IDT All rights reserved. 43 of 43

PDF Datasheet Preview

DAC1005D750

Dual 10-bit DAC, up to 750 Msps 4x and 8x interpolating

The DAC1005D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter DAC with selectable or interpolating filters optimized for multi-carrier wireless transmitters.

Thanks to its digital on-chip modulation, the DAC1005D750 allows the complex I and Q inputs to be converted from BaseBand BB to IF. The mixing frequency is adjusted via a Serial Peripheral Interface SPI with a 32-bit Numerically Controlled Oscillator NCO and the phase is controlled by a 16-bit register.

Two modes of operation are available separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched.

A and clock multiplier enables the DAC1005D750 to provide the appropriate internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use of an external high frequency clock. The voltage regulator enables adjustment of the output full-scale current.

Dual 10-bit resolution

IMD3 74 dBc fs = Msps;
750 Msps maximum update rate
fo = 140 MHz ACPR 64 dBc 2-carrier WCDMA;
fs = Msps fo = MHz Selectable or interpolation filters Typical W power dissipation at
interpolation, PLL off and 740 Msps

Input data rate up to 185 Msps

Power-down and Sleep modes

Very low noise cap-free integrated PLL Differential scalable output current from
mA to 22 mA
32-bit programmable NCO frequency On-chip V reference

Dual port or Interleaved data modes External analog offset control
10-bit auxiliary DACs

V and V power supplies

Internal digital offset control

LVDS compatible clock

Inverse x / sin x function

Two’s complement or binary offset Fully compatible SPI port
data format

V/3.3 V CMOS input data buffers Industrial temperature range from
C to +85 C

Integrated Device Technology

DAC1005D750

Dual 10-bit DAC, up to 750 Msps 4x and 8x interpolating

Wireless infrastructure LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication LMDS/MMDS, point-to-point Direct Digital Synthesis DDS Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment ATE
Ordering information
Table Ordering information

Type number

Package

Name

DAC1005D750HW

HTQFP100
plastic thermal enhanced thin quad flat package 100 leads body 14 1 mm exposed die pad

Version SOT638-1

DAC1005D750 5

IDT All rights reserved.
2 of 43
x xx x xxx

Block diagram

Integrated Device Technology

DAC1005D750 5

DAC1005D750

Dual 10-bit DAC, up to 750 Msps 4x and 8x interpolating

SCS_N

SDIO

SCLK
62 63 65 64 SPI

DAC1005D750

I0 to I9
18 to 25, 28, 29

LATCH I

FIR1 2x

FIR2 2x

FIR3 2x
dual port/ interleaved data modes

Q0 to Q9
41, 42, 45 to 48, 51 to 54
8 CLKP
9 CLKN

LATCH Q

FIR1 2x

FIR2 2x

FIR3 2x

CLOCK GENERATOR/PLL

Fig Block diagram

RESET_N SYNCP
13 SYNCN
Ordering information 2

Block diagram 3

Pinning information 4 Pinning 4 Pin description 5

Limiting values. 8

Thermal characteristics 8

Characteristics 9

Application information. 14 General description 14 Serial peripheral interface. 14 Protocol description 14 SPI timing description 15 Detailed descriptions of registers 17 Detailed register descriptions 19 Recommended configuration 24 Input data 24 Dual-port mode 24 Interleaved mode 25 Input clock 26 Timing 26 Timing when using the internal PLL on 27 Timing when using an external PLL off 27

FIR filters 27 Quadrature modulator and Numerically Controlled Oscillator NCO 28 NCO in 32-bit 29 Low-power NCO 29 Minus_3dB function 29 x / sin x 29 DAC transfer function. 30 Full-scale current 30 Regulation 30 Full-scale current adjustment. 31 Digital offset adjustment. 32 Analog output. 33 Auxiliary DACs 34 Output configuration. 34 Basic output configuration 34 DC interface to an Analog Quadrature Modulator AQM 35 AC interface to an Analog Quadrature Modulator AQM 37 Power and grounding. 38

Package outline. 39

Abbreviations 40

Glossary. 41

Contact information 42

Contents. 43

DAC1005D750 5

IDT All rights reserved.
43 of 43

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Datasheet ID: DAC1005D750HW/C1:5 636936