DAC1005D650HW/C1:5

DAC1005D650HW/C1:5 Datasheet

DAC1005D650

Part	Datasheet
DAC1005D650HW/C1:5	DAC1005D650HW/C1:5 (pdf)

PDF Datasheet Preview
DAC1005D650 Dual 10-bit DAC, up to 650 Msps and interpolating The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter DAC with selectable or interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q inputs to be converted up from BaseBand BB to IF. The mixing frequency is adjusted using a Serial Peripheral Interface SPI with a 32-bit Numerically Controlled Oscillator NCO . The phase is controlled by a 16-bit register. Two modes of operation are available separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1005D650 also includes a and clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. Dual 10-bit resolution 650 Msps maximum update rate Selectable or interpolation IMD3 79 dBc fs = 640 Msps fo = 96 MHz SFDR 75 dBc fdata = 80 MHz; fs = 640 Msps fo = 19 MHz PLL on Typical W power dissipation at filters interpolation Input data rate up to 160 Msps Power-down and Sleep modes Very low noise cap-free integrated PLL Differential scalable output current from mA to 20 mA 32-bit programmable NCO frequency On-chip V reference Dual-port or Interleaved data modes External analog offset control 10-bit auxiliary DACs V and V power supplies Internal digital offset control LVDS compatible clock Inverse sin x / x function Two’s complement or binary offset Fully compatible SPI port data format V CMOS input buffers Industrial temperature range from C to +85 C Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps and interpolating Wireless infrastructure LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication LMDS/MMDS, point-to-point Direct Digital Synthesis DDS Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment ATE Ordering information Table Ordering information Type number Package Name DAC1005D650HW-C1 HTQFP100 plastic thermal enhanced thin quad flat package 100 leads body 14 1 mm exposed die pad Version SOT638-1 DAC1005D650 4 IDT All rights reserved. 2 of 41 x xx x xxx Block diagram Integrated Device Technology DAC1005D650 4 DAC1005D650 Dual 10-bit DAC, up to 650 Msps and interpolating I0 to I9 18 to 25, 28, 29 dual port/ interleaved data modes Q0 to Q9 41, 42 45 to 48, 51 to 54 CLKP 8 CLKN 9 Fig Block diagram SCS_N SDIO SCLK 62 63 65 64 SPI DAC1005D650 LATCH I FIR1 2x FIR2 2x FIR3 2x LATCH Q FIR1 2x FIR2 2x FIR3 2x CLOCK GENERATOR/ PLL 66 RESET_N NCO cos sin mixer + − mixer Ordering information 2 Block diagram 3 Pinning information 4 Pinning 4 Pin description 5 Limiting values. 8 Thermal characteristics 8 Characteristics 9 Application information. 13 General description 13 Serial interface SPI 13 Protocol description 13 SPI timing description 14 Detailed descriptions of registers 15 Registers detailed description. 17 Input data 21 Dual-port mode 21 Interleaved mode 21 Input clock 22 Timing 23 FIR filters 24 Quadrature modulator and NCO 26 NCO in 32-bit 26 Low-power NCO 26 Minus 3 dB 26 x / sin x 26 DAC transfer function. 27 Full-scale current 28 Regulation 28 Full-scale current adjustment. 28 Digital offset adjustment. 29 Analog output. 30 Auxiliary DACs 31 Output configuration. 32 Basic output configuration 32 DC interface to an AQM. 32 AC interface to an AQM 35 Power and grounding. 35 Alternative parts 36 Package outline. 37 Abbreviations 38 Glossary. 39 Contact information 40 Contents. 41 DAC1005D650 4 IDT All rights reserved. 41 of 41

PDF Datasheet Preview

DAC1005D650

Dual 10-bit DAC, up to 650 Msps and interpolating

The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter DAC with selectable or interpolating filters optimized for multi-carrier wireless transmitters.

Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q inputs to be converted up from BaseBand BB to IF. The mixing frequency is adjusted using a Serial Peripheral Interface SPI with a 32-bit Numerically Controlled Oscillator NCO . The phase is controlled by a 16-bit register.

Two modes of operation are available separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched.

The DAC1005D650 also includes a and clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current.

Dual 10-bit resolution 650 Msps maximum update rate

Selectable or interpolation

IMD3 79 dBc fs = 640 Msps fo = 96 MHz SFDR 75 dBc fdata = 80 MHz;
fs = 640 Msps fo = 19 MHz PLL on Typical W power dissipation at
filters
interpolation

Input data rate up to 160 Msps

Power-down and Sleep modes

Very low noise cap-free integrated PLL Differential scalable output current from
mA to 20 mA
32-bit programmable NCO frequency On-chip V reference

Dual-port or Interleaved data modes External analog offset control
10-bit auxiliary DACs

V and V power supplies

Internal digital offset control

LVDS compatible clock

Inverse sin x / x function

Two’s complement or binary offset Fully compatible SPI port
data format

V CMOS input buffers

Industrial temperature range from
C to +85 C

Integrated Device Technology

DAC1005D650

Dual 10-bit DAC, up to 650 Msps and interpolating

Wireless infrastructure LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication LMDS/MMDS, point-to-point Direct Digital Synthesis DDS Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment ATE
Ordering information
Table Ordering information

Type number

Package

Name

DAC1005D650HW-C1 HTQFP100
plastic thermal enhanced thin quad flat package 100 leads body 14 1 mm exposed die pad

Version SOT638-1

DAC1005D650 4

IDT All rights reserved.
2 of 41
x xx x xxx

Block diagram

Integrated Device Technology

DAC1005D650 4

DAC1005D650

Dual 10-bit DAC, up to 650 Msps and interpolating

I0 to I9
18 to 25, 28, 29
dual port/ interleaved data modes

Q0 to Q9
41, 42 45 to 48, 51 to 54

CLKP 8 CLKN 9

Fig Block diagram

SCS_N

SDIO

SCLK
62 63 65 64 SPI

DAC1005D650

LATCH I

FIR1 2x

FIR2 2x

FIR3 2x

LATCH Q

FIR1 2x

FIR2 2x

FIR3 2x

CLOCK GENERATOR/ PLL
66 RESET_N

NCO cos sin
mixer
+ − mixer
Ordering information 2

Block diagram 3

Pinning information 4 Pinning 4 Pin description 5

Limiting values. 8

Thermal characteristics 8

Characteristics 9

Application information. 13 General description 13 Serial interface SPI 13 Protocol description 13 SPI timing description 14 Detailed descriptions of registers 15 Registers detailed description. 17 Input data 21 Dual-port mode 21 Interleaved mode 21 Input clock 22 Timing 23 FIR filters 24

Quadrature modulator and NCO 26 NCO in 32-bit 26 Low-power NCO 26 Minus 3 dB 26 x / sin x 26 DAC transfer function. 27 Full-scale current 28 Regulation 28 Full-scale current adjustment. 28 Digital offset adjustment. 29 Analog output. 30 Auxiliary DACs 31 Output configuration. 32 Basic output configuration 32 DC interface to an AQM. 32 AC interface to an AQM 35 Power and grounding. 35 Alternative parts 36

Package outline. 37

Abbreviations 38

Glossary. 39

Contact information 40

Contents. 41

DAC1005D650 4

IDT All rights reserved.
41 of 41

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Datasheet ID: DAC1005D650HW/C1:5 636935