ADC1003S030TS/C1,1

ADC1003S030TS/C1,1 Datasheet

ADC1003S030/040/050

Part	Datasheet
ADC1003S030TS/C1,1	ADC1003S030TS/C1,1 (pdf)

Related Parts	Information
ADC1003S040TS/C1,1	ADC1003S040TS/C1,1
ADC1003S050TS/C1,1	ADC1003S050TS/C1,1

PDF Datasheet Preview
ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters ADC for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic TTL and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device includes an internal voltage reference regulator. If the application requires that the reference is driven via external sources the recommendation is to use one of the ADC1004S030/040/050 family. 10-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range effective bits at MHz full-scale input at fclk = 40 MHz No missing codes guaranteed In-Range IR CMOS output Levels TTL and CMOS compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed Internal reference voltage regulator Power dissipation only 235 mW typical Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required High-speed analog-to-digital conversion for Video data digitizing Radar Transient signal analysis Global Positioning System GPS receiver modulators Integrated Design Technology ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator Cellular based stations Barcode scanner Medical imaging Quick reference data Table Quick reference data VCCA = V3 to V4 = V to V VCCD = V11 to V12 and V28 to V27 = V to V VCCO = V13 to V14 = V to V AGND and DGND shorted together Tamb = 0 C to 70 C typical values measured at VCCA = VCCD = 5 V and VCCO = V CL = 15 pF and Tamb = 25C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current fclk = 40 MHz ramp input integral non-linearity fclk = 40 MHz; ramp input differential non-linearity fclk = 40 MHz ramp input fclk max maximum clock frequency ADC1003S030TS ADC1003S040TS ADC1003S050TS Ptot total power dissipation fclk = 40 MHz; ramp input 235 305 mW Ordering information Table Ordering information Type number Package Name ADC1003S030TS SSOP28 ADC1003S040TS SSOP28 ADC1003S050TS SSOP28 plastic shrink small outline package 28 leads body width mm plastic shrink small outline package 28 leads body width mm plastic shrink small outline package 28 leads body width mm Version Sampling frequency MHz SOT341-1 30 SOT341-1 40 SOT341-1 50 ADC1003S030_040_050_3 IDT All rights reserved. 2 of 19 Integrated Design Technology Block diagram ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator VCCA 3 DEC 5 REFERENCE VOLTAGE REGULATOR CLK 1 CLOCK DRIVER analog voltage input Rlad ANALOG - TO - DIGITAL CONVERTER LATCHES VCCD2 CMOS OUTPUTS 25 D9 24 D8 23 D7 22 D6 21 D5 20 D4 19 D3 18 D2 17 D1 16 D0 MSB data outputs LSB 13 VCCO ADC1003S030/040/050 4 AGND analog ground 12 DGND2 digital ground IN-RANGE LATCH Ordering information 2 Application diagram 15 Block diagram 3 Alternative parts 16 Pinning information 4 13 Package outline. 17 Pinning 4 14 Pin description 4 15 Contact information 18 Limiting values. 5 16 Contents. 19 ADC1003S030_040_050_3 IDT All rights reserved. 19 of 19

PDF Datasheet Preview

ADC1003S030/040/050

Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz, with voltage regulator

The ADC1003S030/040/050 are a family of 10-bit high-speed low-power Analog-to-Digital Converters ADC for professional video and other applications. They convert the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic TTL and CMOS compatible, although a low-level sine wave clock input signal is allowed.

The device includes an internal voltage reference regulator. If the application requires that the reference is driven via external sources the recommendation is to use one of the ADC1004S030/040/050 family.
10-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range
effective bits at MHz full-scale input at fclk = 40 MHz No missing codes guaranteed In-Range IR CMOS output Levels TTL and CMOS compatible digital inputs 3 V to 5 V CMOS digital outputs Low-level AC clock input signal allowed Internal reference voltage regulator Power dissipation only 235 mW typical Low analog input capacitance, no buffer amplifier required No sample-and-hold circuit required

High-speed analog-to-digital conversion for Video data digitizing Radar Transient signal analysis Global Positioning System GPS receiver modulators

Integrated Design Technology

ADC1003S030/040/050

Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator

Cellular based stations Barcode scanner Medical imaging

Quick reference data

Table Quick reference data VCCA = V3 to V4 = V to V VCCD = V11 to V12 and V28 to V27 = V to V VCCO = V13 to V14 = V to V AGND and DGND shorted together Tamb = 0 C to 70 C typical values measured at VCCA = VCCD = 5 V and VCCO = V CL = 15 pF and Tamb = 25C unless otherwise specified.

Symbol Parameter

Conditions

Min Typ Max Unit

VCCA VCCD VCCO ICCA ICCD ICCO
analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current
fclk = 40 MHz ramp input
integral non-linearity fclk = 40 MHz;
ramp input
differential non-linearity fclk = 40 MHz ramp input
fclk max
maximum clock frequency

ADC1003S030TS

ADC1003S040TS

ADC1003S050TS

Ptot
total power dissipation fclk = 40 MHz;
ramp input
235 305 mW
Ordering information
Table Ordering information

Type number

Package

Name

ADC1003S030TS SSOP28 ADC1003S040TS SSOP28 ADC1003S050TS SSOP28
plastic shrink small outline package 28 leads body width mm
plastic shrink small outline package 28 leads body width mm
plastic shrink small outline package 28 leads body width mm

Version

Sampling frequency MHz

SOT341-1 30

SOT341-1 40

SOT341-1 50

ADC1003S030_040_050_3

IDT All rights reserved.
2 of 19

Integrated Design Technology

Block diagram

ADC1003S030/040/050

Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator

VCCA 3

DEC 5

REFERENCE VOLTAGE

REGULATOR

CLK 1

CLOCK DRIVER
analog voltage input

Rlad

ANALOG - TO - DIGITAL CONVERTER

LATCHES

VCCD2

CMOS OUTPUTS
25 D9 24 D8 23 D7 22 D6 21 D5 20 D4 19 D3 18 D2 17 D1 16 D0

MSB data outputs LSB
13 VCCO

ADC1003S030/040/050
4 AGND
analog ground
12 DGND2
digital ground

IN-RANGE LATCH
Ordering information 2

Application diagram 15

Block diagram 3

Alternative parts 16

Pinning information 4 13

Package outline. 17

Pinning 4 14

Pin description 4 15

Contact information 18

Limiting values. 5 16

Contents. 19

ADC1003S030_040_050_3

IDT All rights reserved.
19 of 19

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Datasheet ID: ADC1003S030TS/C1,1 636924