ADC0801S040TS/C1,1

ADC0801S040TS/C1,1 Datasheet

ADC0801S040

Part	Datasheet
ADC0801S040TS/C1,1	ADC0801S040TS/C1,1 (pdf)

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ADC0801S040 Single 8 bits ADC, up to 40 MHz The ADC0801S040 is an 8-bit universal analog-to-digital converter ADC for video and general purpose applications. It converts the analog input signal from V to V into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are CMOS/Transistor-Transistor Logic TTL compatible. A sleep mode allows reduction of the device power consumption to 4 mW. 8-bit resolution Operation between V and V Sampling rate up to 40 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range effective bits at MHz full-scale input at fclk = 40 MHz CMOS/TTL compatible digital inputs and outputs External reference voltage regulator Power dissipation only 30 mW typical value Low analog input capacitance, no buffer amplifier required Sleep mode 4 mW No sample-and-hold circuit required Video data digitizing Camera Camcorder Radio communication Car alarm system Integrated Device Technology ADC0801S040 Single 8 bits ADC, up to 40 MHz Quick reference data Table Quick reference data VDDA = V5 to V6 = V VDDD = V3 to V4 = V VDDO = V20 to V11 = V VSSA, VSSD and VSSO shorted together Vi a p-p = V CL = 20 pF Tamb = 0 C to 70 C typical values measured at Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDDD digital supply voltage VDDO output supply voltage IDDA supply voltage difference analog supply current VDDA VDDD VDDO IDDD digital supply current IDDO INL output supply current integral non-linearity fclk = 40 MHz ramp input CL = 20 pF ramp input see Figure 6 differential non-linearity ramp input see Figure 7 fclk max maximum clock frequency Ptot total power VDDA = VDDD = VDDO = V dissipation Ordering information Table Ordering information Type number Package Name ADC0801S040TS SSOP20 Description plastic shrink small outline package 20 leads body width mm Version SOT266-1 3ADC0801S040_3 IDT All rights reserved. 2 of 18 Integrated Device Technology Block diagram ADC0801S040 Single 8 bits ADC, up to 40 MHz VDDA 5 CLK 1 VDDD 3 RT 10 CLOCK DRIVER ADC0801S040 2 SLEEP analog VI 9 voltage input Rlad ANALOG - TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS 19 D7 18 D6 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0 MSB data outputs LSB VDDO 6 VSSA analog ground Fig Block diagram 11 VSSO 4 VSSD output ground digital ground 014aaa495 3ADC0801S040_3 IDT All rights reserved. 3 of 18 Integrated Device Technology Pinning information Ordering information 2 Application diagrams 15 Block diagram 3 13 Package outline. 16 Pinning information 4 14 Pinning 4 15 Pin description 4 16 Limiting values. 5 Contact information 17 Contents. 18 3ADC0801S040_3 IDT All rights reserved. 18 of 18

PDF Datasheet Preview

ADC0801S040

Single 8 bits ADC, up to 40 MHz

The ADC0801S040 is an 8-bit universal analog-to-digital converter ADC for video and general purpose applications. It converts the analog input signal from V to V into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are CMOS/Transistor-Transistor Logic TTL compatible. A sleep mode allows reduction of the device power consumption to 4 mW.
8-bit resolution Operation between V and V Sampling rate up to 40 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range effective bits
at MHz full-scale input at fclk = 40 MHz CMOS/TTL compatible digital inputs and outputs External reference voltage regulator Power dissipation only 30 mW typical value Low analog input capacitance, no buffer amplifier required Sleep mode 4 mW No sample-and-hold circuit required

Video data digitizing Camera Camcorder Radio communication Car alarm system

Integrated Device Technology

ADC0801S040

Single 8 bits ADC, up to 40 MHz

Quick reference data

Table Quick reference data

VDDA = V5 to V6 = V VDDD = V3 to V4 = V VDDO = V20 to V11 = V VSSA, VSSD and VSSO shorted together Vi a p-p = V CL = 20 pF Tamb = 0 C to 70 C typical values measured at Tamb = 25 C unless otherwise specified.

Symbol Parameter Conditions

Min Typ Max Unit

VDDA
analog supply voltage

VDDD
digital supply voltage

VDDO
output supply voltage

IDDA
supply voltage difference
analog supply current

VDDA VDDD VDDO

IDDD
digital supply
current

IDDO INL
output supply current
integral non-linearity
fclk = 40 MHz ramp input CL = 20 pF ramp input see Figure 6
differential non-linearity
ramp input see Figure 7
fclk max
maximum clock frequency

Ptot
total power

VDDA = VDDD = VDDO = V
dissipation
Ordering information
Table Ordering information

Type number

Package

Name

ADC0801S040TS

SSOP20

Description plastic shrink small outline package 20 leads body width mm

Version SOT266-1
3ADC0801S040_3

IDT All rights reserved.
2 of 18

Integrated Device Technology

Block diagram

ADC0801S040

Single 8 bits ADC, up to 40 MHz

VDDA 5

CLK 1

VDDD 3

RT 10

CLOCK DRIVER

ADC0801S040
2 SLEEP
analog VI 9 voltage input

Rlad

ANALOG - TO - DIGITAL CONVERTER

LATCHES

CMOS OUTPUTS
19 D7 18 D6 17 D5 16 D4 15 D3 14 D2 13 D1 12 D0

MSB data outputs LSB

VDDO
6 VSSA analog ground

Fig Block diagram
11 VSSO
4 VSSD
output ground digital ground
014aaa495
3ADC0801S040_3

IDT All rights reserved.
3 of 18

Integrated Device Technology

Pinning information
Ordering information 2

Application diagrams 15

Block diagram 3 13

Package outline. 16

Pinning information 4 14

Pinning 4 15

Pin description 4 16

Limiting values. 5

Contact information 17 Contents. 18
3ADC0801S040_3

IDT All rights reserved.
18 of 18

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Datasheet ID: ADC0801S040TS/C1,1 636922