QWLXT9785BC.D0-998807

QWLXT9785BC.D0-998807 Datasheet

LXT9785/9785E QWLXT9785BC.D0-998807 RoHS 6

Part	Datasheet
QWLXT9785BC.D0-998807	QWLXT9785BC.D0-998807 (pdf)

Related Parts	Information
WBLXT9785HC.D0-865112	WBLXT9785HC.D0-865112

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Cortina LXT9785 and LXT9785E Advanced 8-Port 10/ 100 Mbps PHY Transceivers Datasheet The Cortina LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces SMII/SS-SMII and Reduced Media Independent Interface RMII for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment DTE requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT9785E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone. Each network port can provide a twisted-pair TP or Low-Voltage Positive Emitter Coupled Logic LVPECL interface. The twisted-pair interface supports 10 Mbps and 100 Mbps 10BASE-T and 100BASE-TX Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps 100BASE-FX Ethernet over fiber-optic media. The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single V power supply. - Enterprise switches - IP telephony switches Product Features - Storage Area Networks - Multi-port Network Interface Cards NICs - Eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters. - 100BASE-FX fiber-optic capability on all ports. - V operation. - Low power consumption 250 mW per port typical. - Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. - Auto MDI/MDIX crossover capability. - Proprietary Optimal Signal Processing architecture improves SNR by 3 dB over ideal analog filters. - Optimized for dual-high stacked RJ-45 applications. - MDIO sectionalization into 2x4 or 1x8 configurations. - Supports both auto-negotiation systems and legacy systems without auto-negotiation capability. - Robust baseline wander correction. - Configurable through the MDIO port or external control pins. - JTAG boundary scan. - 208-pin PQFP LXT9785HC, LXT9785EHC, LXT9785HE. - 241-ball BGA LXT9785BC, LXT9785EBC. - 196-ball BGA LXT9785MBC includes DTE detection similar to the LXT9785E - DTE detection for remote powering applications LXT9785E and LXT9785MBC only . - Extended temperature operation of -40 oC to +85 oC LXT9785E only . Contents Contents What You Will Find in This Document Related Documents Block Diagram Pin/Ball Assignments and Signal Descriptions PQFP Pin Assignments PQFP Pin Assignments RMII Configuration PQFP Pin Assignments SMII PQFP Pin Assignments SS-SMII PQFP Signal Descriptions Signal Name Conventions PQFP Signal Descriptions RMII, SMII, and SS-SMII Configurations..................36 BGA23 Ball RMII BGA23 Ball List SMII BGA23 Ball List SS-SMII BGA23 Ball List BGA23 Signal Descriptions Signal Name Conventions Signal Descriptions RMII, SMII, and SS-SMII BGA15 Ball BGA15 Ball BGA15 Signal Descriptions Signal Name Conventions Signal Descriptions SMII and SS-SMII Configurations Functional Introduction OSP Architecture Comprehensive Functionality Interface Descriptions 10/100 Network Twisted-Pair Interface MDI Crossover Fiber Media Independent Interface MII Interfaces Global MII Mode Select Internal Loopback RMII Data Serial Media Independent Interface SMII and Source Synchronous- Serial Media Independent Interface SS-SMII Source Synchronous-Serial Media Independent Interface Configuration Management Interface MII Isolate MDIO Management Interface MII Top Label Markings Ordering Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 5 Figures Figures 1 Block Diagram 2 RMII 208-Pin PQFP Assignments 3 SMII 208-Pin PQFP Assignments 4 SS-SMII 208-Pin PQFP Assignments 5 241-Ball BGA23 Assignments Top View 6 196-Ball BGA15 Assignments Top View 7 Interface Signals 8 Internal Loopback 9 Management Interface Read Frame Structure 10 Management Interface Write Frame Structure 11 Port Address 12 Interrupt 13 Initialization 14 Auto-Negotiation Operation 15 Typical SMII 16 Typical SMII Quad Sectionalization 17 100 Mbps Serial MII Data Flow 18 Serial MII Transmit Synchronization 19 Serial MII Receive Synchronization 20 Typical SS-SMII 21 Typical SS-SMII Quad Sectionalization 22 SS-SMII Transmit Timing 23 SS-SMII Receive Timing 24 RMII Data 25 Typical RMII 26 Typical RMII Quad 27 100BASE-X Frame 28 Protocol Sublayers 29 Typical IP Telephone System 30 Cortina LXT9785E Negotiation Flow 31 LED Pulse Stretching 32 RMII Programmable Out-of-Band Signaling 33 LED Circuit 34 Power and Ground Supply Connections 35 Typical Twisted-Pair Interface 36 Recommended LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry...................167 37 Recommended LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry......................168 38 ON Semiconductor Triple PECL-to-LVPECL Translator 39 SMII - 100BASE-TX Receive Timing 40 SMII - 100BASE-TX Transmit Timing 41 SMII - 100BASE-FX Receive Timing 42 SMII - 100BASE-FX Transmit Timing 43 SMII - 10BASE-T Receive Timing 44 SMII - 10BASE-T Transmit Timing 45 SS-SMII - 100BASE-TX Receive Timing 46 SS-SMII - 100BASE-TX Transmit Timing 47 SS-SMII - 100BASE-FX Receive Timing 48 SS-SMII - 100BASE-FX Transmit Timing Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 6 Figures 49 SS-SMII - 10BASE-T Receive Timing 50 SS-SMII - 10BASE-T Transmit Timing 51 RMII - 100BASE-TX Receive 52 RMII - 100BASE-TX Transmit 53 RMII - 100BASE-FX Receive 54 RMII - 100BASE-FX Transmit 55 RMII - 10BASE-T Receive Timing 56 RMII - 10BASE-T Transmit Timing 57 Auto-Negotiation and Fast Link Pulse Timing 58 Fast Link Pulse Timing 59 MDIO Write Timing MDIO Sourced by MAC 60 MDIO Read Timing MDIO Sourced by PHY 61 Power-Up 62 RESET_L Recovery 63 PHY Identifier Bit Mapping 64 208-Pin PQFP Plastic Package Specification 65 241-Ball BGA23 Package Specificationss - Top/Side Views 66 241-Ball BGA23 Package Specificationss - Bottom View LXT9785BC 67 196-Ball BGA15 Package Specs - Top/Side Views 68 196-Ball BGA15 Package Bottom View LXT9785MBC 69 Example of Top Marking Information Labeled as Cortina Systems, Inc. 70 Example of Top Marking Information Labeled as Intel Corporation* 71 Example of Top Marking Information Labeled as Level One Communications* 72 Ordering Information - Sample Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 7 Tables Tables 1 Signal Type Descriptions 2 RMII PQFP Pin List 3 SMII PQFP Pin 4 SS-SMII PQFP Pin 5 RMII Signal Descriptions PQFP 6 SMII/SS-SMII Common Signal Descriptions 7 SMII Specific Signal Descriptions PQFP 8 SS-SMII Specific Signal Descriptions PQFP 9 MDIO Control Interface Signals PQFP 10 Signal Detect PQFP 11 Network Interface Signal Descriptions PQFP 12 JTAG Test Signal Descriptions PQFP 13 Miscellaneous Signal Descriptions PQFP 14 LED Signal Descriptions PQFP 15 Power Supply Signal Descriptions PQFP 16 Unused/Reserved Pins PQFP 17 Receive FIFO Depth Considerations 18 RMII BGA23 Ball List in Alphanumeric Order by Signal Name 19 RMII BGA23 Ball List in Alphanumeric Order by Ball Location 20 SMII BGA23 Ball List in Alphanumeric Order by Signal 21 SMII BGA23 Ball List in Alphanumeric Order by Ball 22 SS-SMII BGA23 Ball List in Alphanumeric Order by Signal 23 SS-SMII BGA23 Ball List in Alphanumeric Order by Ball 24 RMII Signal Descriptions 25 SMII/SS-SMII Common Signal Descriptions BGA23 26 SMII Specific Signal Descriptions BGA23 27 SS-SMII Specific Signal Descriptions BGA23 28 MDIO Control Interface Signals BGA23 29 Signal Detect 30 Network Interface Signal Descriptions BGA23 31 JTAG Test Signal Descriptions BGA23 32 Miscellaneous Signal Descriptions BGA23 33 LED Signal Descriptions BGA23 34 Power Supply Signal Descriptions BGA23 35 Unused/Reserved Pins BGA23 36 Receive FIFO Depth 37 LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name 38 LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location SMII/SS-SMII 39 BGA15 Signal Descriptions 40 MDIX Selection 41 MII Mode 42 Global Hardware Configuration Settings 43 SMII Signal Summary 44 RX Status Encoding Bit Definitions 45 SS-SMII 46 4B/5B Coding 47 DTE Terms 48 Next Page Message #5 Code Word Definitions Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 8 Tables 49 BSR Mode of Operation 50 Supported JTAG Instructions 51 Magnetics Requirements 52 Absolute Maximum Ratings 53 Operating Conditions 54 Digital I/O DC Electrical Characteristics VCCIO = V +/- 5% 55 Digital I/O DC Electrical Characteristics VCCIO = V +/- 5% 56 Digital I/O DC Electrical Characteristics SD Pins 57 Required Clock Characteristics 58 100BASE-TX Transceiver 59 100BASE-FX Transceiver 60 10BASE-T Transceiver Characteristics 61 SMII - 100BASE-TX Receive Timing Parameters 62 SMII - 100BASE-TX Transmit Timing Parameters 63 SMII - 100BASE-FX Receive Timing Parameters 64 SMII - 100BASE-FX Transmit Timing Parameters 65 SMII - 10BASE-T Receive Timing 66 SMII-10BASE-T Transmit Timing 67 SS-SMII - 100BASE-TX Receive Timing Parameters 68 SS-SMII - 100BASE-TX Transmit Timing 69 SS-SMII - 100BASE-FX Receive Timing Parameters 70 SS-SMII - 100BASE-FX Transmit Timing Parameters 71 SS-SMII - 10BASE-T Receive Timing 72 SS-SMII - 10BASE-T Transmit Timing 73 RMII - 100BASE-TX Receive Timing Parameters 74 RMII - 100BASE-TX Transmit Timing Parameters 75 RMII - 100BASE-FX Receive Timing Parameters 76 RMII - 100BASE-FX Transmit Timing Parameters 77 RMII - 10BASE-T Receive Timing Parameters 78 RMII - 10BASE-T Transmit Timing Parameters 79 Auto-Negotiation and Fast Link Pulse Timing Parameters 80 MDIO Timing Parameters 81 Power-Up Timing Parameters 82 RESET_L Recovery Timing Parameters 83 Register 84 Control Register Address 0 85 Status Register Address 1 86 PHY Identification Register 1 Address 2 87 PHY Identification Register 2 Address 3 88 Auto-Negotiation Advertisement Register Address 4 89 Auto-Negotiation Link Partner Base Page Ability Register Address 5 90 Auto-Negotiation Expansion Register Address 6 91 Auto-Negotiation Next Page Transmit Register Address 7 92 Auto-Negotiation Link Partner Next Page Receive Register Address 93 Port Configuration Register Address 16, Hex 10 94 Quick Status Register Address 17, Hex 11 95 Interrupt Enable Register Address 18, Hex 96 Interrupt Status Register Address 19, Hex 97 LED Configuration Register Address 20, Hex 14 98 Receive Error Count Register Address 21, Hex Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 9 Tables 99 RMII Out-of-Band Signaling Register Address 25, Hex 19 100 Trim Enable Register Address 27, Hex 1B 101 Cable Diagnostics Register Address 29, Hex 102 Register Bit Map 103 241-Ball BGA23 Package Dimensions 104 196-Ball BGA15 Package Dimensions LXT9785MBC 105 Product Information Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 10 Page 48 page 93 page 123 page 126 page 192 page 195 page 200 page 217 page 219 Modified signal description text for VCCPECL in Table 15, Power Supply Signal Descriptions PQFP. Modified signal description text for VCCPECL in Table 34, Power Supply Signal Descriptions BGA23. Added note under Section RxCLK Signal SS-SMII Only . Modified CFG 1,2,3 settings for Register bit when set to “1” in Table 42, Global Hardware Configuration Settings. Added table note 6 to Register bit Loopback in Table 84, Control Register Address 0 Modified table note 6 for Register bit in Table 88, Auto-Negotiation Advertisement Register Address Modified note in Register bit Collision Status in Table 94, Quick Status Register Address 17, Hex Added Section Top Label Markings. Modified Section Ordering Information Table 105, Product Information and Figure 72, Ordering Information Sample. Page 1 43 88 53 229 230 Modified 196-Ball BGA and DTE Detection bullets under Product Features. Added table note 3 regarding LINKHOLD to Table 13, Miscellaneous Signal Descriptions PQFP, on page Added table note 3 regarding LINKHOLD to Table 32, Miscellaneous Signal Descriptions BGA23, on page Modified Table 18 “RMII BGA23 Ball List in Alphanumeric Order by Signal Name” through Table 23 “SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location” for ball, type, and reference page corrections. Modified Table 104 “Product Information” [added new packaging information]. Modified Figure 69 “Ordering Information - Sample” [changed Internal Package Designator for B and E, and added the GD and definition under Package Designator . Page All 229 Globally added LEDn_3 to BGA15. Added Figure 68 “Cortina LXT9785MBC 196-Ball BGA15 Package Bottom View”. Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 11 21 22 26 27 31 32 36 40 43 50 51 82 86 90 97 116 117 119 120 121 Modified Figure 2 “Cortina LXT9785 and Cortina LXT9785E RMII 208-Pin PQFP Assignments”. Modified Table 2 “Cortina LXT9785/LXT9785E RMII PQFP Pin List”. Modified Figure 3 “Cortina LXT9785/LXT9785E SMII 208-Pin PQFP Assignments”. Modified Table 3 “Cortina LXT9785/LXT9785E SMII PQFP Pin List”. Modified Figure 4 “Cortina LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments”. Modified Table 4 “Cortina LXT9785/LXT9785 SS-SMII PQFP Pin List”. Modified Table 5 “Cortina LXT9785/LXT9785E RMII Signal Descriptions PQFP”. Modified Table 8 “Cortina LXT9785/LXT9785E SS-SMII Specific Signal Descriptions PQFP”. Modified Table 13 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions PQFP”. Modified Table 16 “Cortina LXT9785/LXT9785E Unused/Reserved Pins PQFP”. Replaced old Figures 5, 6, and 7 with Figure 5 “Cortina LXT9785/LXT9785E 241-Ball BGA23 Assignments Top View ”. Modified Table 18 “Cortina LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name”. Modified Table 19 “Cortina LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location”. Modified Table 20 “Cortina LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name”. Modified Table 21 “Cortina LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location” Modified Table 22 “Cortina LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name”. Modified Table 23 “Cortina LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location”. Modified Table 23 “Cortina LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location”. Modified Table 27 “Cortina LXT9785/LXT9785E SS-SMII Specific Signal Descriptions BGA23”. Modified Table 32 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions BGA23”. Modified Table 35 “Cortina LXT9785/LXT9785E Unused/Reserved Pins BGA23”. Added Section “BGA15 Ball Assignments” including Figure 6 “Cortina LXT9785MBC 196-Ball BGA15 Assignments Top View ”, Table 37 “Cortina LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” through Table 39 “Cortina LXT9785 BGA15 Signal Descriptions”. Added second paragraph under Section “Introduction”. Added note under Section “Sectionalization”. Added note under Table 40 “Cortina LXT9785/LXT9785E MDIX Selection”. Added note under Section “Media Independent Interface MII Interfaces”. Added note to Table 41 “Cortina LXT9785/LXT9785E MII Mode Select”. Modified/added text under Section “Internal Loopback”. Modified text under Section “MII Isolate”. Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 12 123 124 125 127 128 129 130 131 136 141 148 149 150 151 152 153 154 155 157 158 160 161 162 173 176 Section “MDIO Management Interface” Added note under second paragraph. Added last paragraph. Added note under Section “MII Sectionalization”. Added new Section “FIFO Initial Fill Values” Modified paragraph three under Section “Power Requirements”. Added notes under second and last paragraphs under Section “Power-Down Mode”. Modified last bullet under Section “Global Hardware Power Down”. Added last paragraph to Section “Reset”. Modified Table 42 “Cortina LXT9785/LXT9785E Global Hardware Configuration Settings”. Change heading and modified last line under Section “Manual Next Page Exchange”. Section “Link Criteria” Changed scrambler to descrambler in first line. Modified second paragraph. Added two new paragraphs. Added second paragraph under Section “Parallel Detection”. Modified paragraphs under Section “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode”. Changed “1110” to “0101” under Section “Receive Error”. Added note under first paragraph of Section “RMII Operation” Changed “asynchronously” to “synchronously” in second paragraph under Section “Carrier Sense/Data Valid RMII ”. Modified last sentence in first paragraph under Section “Carrier Sense SMII ”. Modified paragraph under Section “Polarity Correction”. Added note under Section “Fiber PMD Sublayer”. Added second paragraph under Section “Far End Fault Indications”. Modified/added text under Section “Preamble Handling”. Modified text under Section “Jabber”. Modified first paragraph under Section “DTE Discovery Process”. Modified Item 1 of Section “Interaction between Processor, MAC, and PHY”. Modified second paragraph under Section “DTE Discovery Process Flow”. Added Section “DTE Discovery Behavior” Added BGA15 information into first paragraph under Section “Per-Port LED Driver Functions”. Added last sentence to first paragraph and note under first paragraph under Section “Out-of-Band Signaling”. Added Section “Cable Diagnostics Overview”. Modified/added text under Section “Implementation Considerations”. Added Section “Link Hold-Off Overview”. Modified Table 52 “Cortina LXT9785/LXT9785E Operating Conditions” Modified Table 58 “Cortina LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics” Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 13 178-195 199 200 201 203 204 205 206 207 209 211 212 213 214 215 216 217 219 226 227 Description Added note to Table 60 “Cortina LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters” through Table 77 “Cortina LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters”. Added table note to Table 60 “Cortina LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters”. Added table note to Table 66 “Cortina LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters”. Added table note to Table 72 “Cortina LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters” Added software power-down and note to Table 80 “Cortina LXT9785/LXT9785E Power-Up Timing Parameters”. Modified paragraphs and added last paragraph under Section “Register Definitions”. Modified Table 82 “Cortina LXT9785/LXT9785E Register Set”. Modified Table 83 “Control Register Address Modified Table 84 “Status Register Address Modified Table 85 “PHY Identification Register 1 Address Modified Table 86 “PHY Identification Register 2 Address 3 ” Modified Table 87 “Auto-Negotiation Advertisement Register Address 4 ” Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register Address Modified Table 89 “Auto-Negotiation Expansion Register Address Modified Table 90 “Auto-Negotiation Next Page Transmit Register Address Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register Address Modified Table 92 “Port Configuration Register Address 16, Hex Register bits Modified Table 93 “Quick Status Register Address 17, Hex Register bit Modified Table 94 “Interrupt Enable Register Address 18, Hex 12 ” Modified Table 95 “Interrupt Status Register Address 19, Hex 13 ” Modified Table 96 “LED Configuration Register Address 20, Hex 14 ” Modified Table 97 “Receive Error Count Register Address 21, Hex Modified Table 98 “RMII Out-of-Band Signaling Register Address 25, Hex Modified Table 99 “Trim Enable Register Address 27, Hex 1B ”. Register bit Added Table 100 “Cable Diagnostics Register Address 29, Hex 1D ”. Modified Table 101 “Cortina LXT9785/LXT9785E Register Bit Map”. Added Figure 102 “Cortina LXT9785MBC 196-Ball BGA15 Package Dimensions” Modified table and figure under Section “Ordering Information”. Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 14 36 42 43 116 119 120 130 131 136 145 146 148 149 150 151 152 153 158 166 170 171 173 174 175 176 Changed "pseudo-ECL PECL " to "Low Voltage Positive Emitter Coupled Logic LVPECL " in the second paragraph, front page. Modified Table 5 “Cortina LXT9785/LXT9785E RMII Signal Descriptions PQFP”. Added last sentence to RXER0 through RXER7 signal description. Modified Table 10 “Cortina LXT9785/LXT9785E Signal Detect PQFP”. Modified Table 11 “Cortina LXT9785/LXT9785E Network Interface Signal Descriptions PQFP”, Modified Table 13 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions PQFP”. Added note to PREASEL signal description. Modified Section “Introduction”. Changed "Pseudo-ECL PECL " to "Low Voltage PECL LVPECL " in the first paragraph, second sentence. Replace text under Section “Fiber Interface”. Modified Section “Internal Loopback”. Modified last sentence under Section “Link Criteria”. Modified text under Section “Parallel Detection”. Added second paragraph. Modified text under Section “Receive Error”. Changed "PECL" to "LVPECL in third paragraph, first sentence under Section “100BASE-X Network Operations”. Modified Figure 28 “Cortina LXT9785/LXT9785E Protocol Sublayers”. Modified Section “Carrier Sense/Data Valid RMII ”. Changed “asynchronously to “synchronously.” Modified paragraph under Section “Polarity Correction”. Replaced text under Section “Fiber PMD Sublayer”. Modified Section “Preamble Handling”. Added text to last paragraph. Modified first sentence under Section “Jabber”. Modified first paragraph of Section “DTE Discovery Process”. Modified Item 1 of Section “Interaction between Processor, MAC, and PHY”. Modified Section “Out-of-Band Signaling”. Added sentence to end of first paragraph. Replaced text under Section “The Fiber Interface”. Replaced Figure 36 “Recommended Cortina LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry”. Replaced Figure 37 “Recommended Cortina LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry”. Modified Table 52 “Cortina LXT9785/LXT9785E Operating Conditions”. Modified Table 53 “Cortina LXT9785/LXT9785E Digital I/O DC Electrical Characteristics VCCIO = V +/- Modified Table 54 “Cortina LXT9785/LXT9785E Digital I/O DC Electrical Characteristics VCCIO = V +/- Added Table 55 “Cortina LXT9785/LXT9785E Digital I/O DC Electrical Characteristics SD Pins”. Modified Table 58 “Cortina LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”. Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 15 Page 200 201 204 205 207 209 211 212 214 215 216 227 Description Modified Table 83 “Control Register Address Modified Table 84 “Status Register Address Modified Table 87 “Auto-Negotiation Advertisement Register Address Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register Address Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register Address Modified Table 92 “Port Configuration Register Address 16, Hex Modified Table 93 “Quick Status Register Address 17, Hex Modified Table 94 “Interrupt Enable Register Address 18, Hex 12 ” Modified Table 95 “Interrupt Status Register Address 19, Hex Changed all references of RO/SC to R/LH. Modified Table 97 “Receive Error Count Register Address 21, Hex Modified Table 98 “RMII Out-of-Band Signaling Register Address 25, Hex Added note to Register bit Modified Table 99 “Trim Enable Register Address 27, Hex 1B ”. Modified Table 103 “Product Information”. Page 1 49 70 110 111 112 114 Added bullet to Product Features Modified Table 12 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions” Added FIFOSEL1 and FIFOSEL0 Added Section “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode” Modified Figure 38 “Recommended Cortina LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry” Added Figure 39 “Recommended Cortina LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry” Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator” Modified Table 28 “Absolute Maximum Ratings” Modified Table 29 “Operating Conditions” Modified Table 31 “Digital I/O DC Electrical Characteristics VCCIO = V +/- 5% ” Output low voltage SD pins Max Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX Receive Timing Parameters” Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX Receive Timing Parameters” Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive Timing Parameters” Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 16 Description Modified Table 69 “Port Configuration Register Address 16, Hex 10 ” Bits and Modified Table 71 “Interrupt Enable Register Address 18, Hex 12 ” Added product ordering table and diagram. Page 1 61 85 93 97 99 102 122 126 128 131 133 140 141 Description Modified and added new language to front page. Reset Modified language in first paragraph. Added new section on DTE discovery. Supported JTAG Instructions table replaced long hit streams with hex. LED Circuit Modified paragraph language. LED Circuit diagram Modified diagram. Replaced Typical Fiber Interface diagram. Required Clock Characteristics table Replaced SMII Input frequency and RMII Input frequency symbol with “f”. Auto-Negotiation and Fast Link Pulse Timing Parameters FLP burst width under Typ = Control Register table Modified table and table notes. PHY Identification Register 2 Address 3 Modified table. PHY Identifier Bit Mapping Modified diagram. Auto-Negotiation Expansion Modified table and table notes. Port Configuration Register table Modified table and table notes. Trim Enable Register Modified table DTE Discovery . Modified Register Bit Map table. Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 17 Introduction Introduction This document contains information on the Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers. What You Will Find in This Document This document contains the following sections • Section Block Diagram, on page 19 • Section Pin/Ball Assignments and Signal Descriptions, on page 20 This section contains pin/ball assignments and signal descriptions for the following Section PQFP Pin Assignments, on page 20 Section PQFP Signal Descriptions, on page 36 Section BGA23 Ball Assignments, on page 51 Section BGA23 Signal Descriptions, on page 79 Section BGA15 Ball Assignments, on page 97 Section BGA15 Signal Descriptions, on page 106 • Section Functional Description, on page 113 • Section Application Information, on page 161 • Section Test Specifications, on page 170 • Section Register Definitions, on page 191 • Section Package Specifications, on page 212 • Section Ordering Information, on page 219 Related Documents Document Cortina LXT9785/LXT9785E Design and Layout Guide Cortina LXT9785/LXT9785E Specification Update Cortina LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers Connecting a PECL/LVPECL Interface IP Telephony and DTE Discovery Using Cortina Ethernet PHYs Document Number 249509 249357 250781 249611 Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 18 Block Diagram Figure 1 Block Diagram Figure 1 provides the LXT9785/LXT9785E block diagram. Block Diagram RMII/SMII Contr ADD_[4:0] MDIO MDC 2 MDINT_L 2 TxDatan LEDn_[3:1]_L RxDatan RX PCS Management / Mode Select Logic & LED Drivers 8-Port Global Functions Clock Generator TX PCS Mgmt Counters Register Set Register Set Parallel/Serial Converter Manchester Encoder 10 Scrambler 100 & Encoder Pulse Shaper Auto Negotiation TP Driver ECL Driver TP / Fiber Out Port LED Drivers Clock Generator Media Select Ordering Information Ordering Information Table 105 and Figure 72 provide product ordering information. Table 105 Product Information Number FWLXT9785BC.D0 PRLXT9785BC.D0 FWLXT9785EBC.D0 PRLXT9785EBC.D0 FWLXT9785BC.C2V PRLXT9785BC.C2V FWLXT9785EBC.C2V PRLXT9785EBC.C2V GDLXT9785MBC.D0 LULXT9785MBC.D0 HBLXT9785HC.D0 WBLXT9785HC.D0 HBLXT9785EHC.D0 WBLXT9785EHC.D0 HBLXT9785HE.D0 WBLXT9785HE.D0 HBLXT9785EHC.C2V WBLXT9785EHC.C2V HBLXT9785HC.C2V WBLXT9785HC.C2V HBLXT9785HE.C2V WBLXT9785HE.C2V Package Type PBGA HQFP Pin Count 241 196 208 RoHS Compliant No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 219 Ordering Information Figure 72 Ordering Information - Sample FW LXT 9785E B C A6 S E001 Build Format E000 =Tray E001 = Tape and reel Qualification Q =Pre-production material S = Production material Temperature Range A = Ambient 0 - 55° C =Commercial 0 - 70° C E = Extended -40 - +85° C Internal Package Designator L = LQFP P = PLCC N = DIP Q = PQFP H = QFP with heat spreader T = TQFP B =BGA E = TBGA K = HSBGA BGA with heat slug xxxx = 3-5 Digit Alphanumeric Product Code Product Prefix LXT =PHYlayer device IXF = Formatting device MAC Package Designator DJ = LQFP FA = TQFP FL = PBGA mm pitch FW =PBGA 1.27mmpitch HB =QFPwithheat spreader HD = QFP with heat slug HG =SOIC S =QFP GC =TBGA N = PLCC LXT9785 = Nominal device LXT9785E = DTE detection feature LXT9785MBC = 196 ball BGA with DTE detection feature Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Page 220 Contact Information Cortina Systems, Inc. 840 W. California Ave Sunnyvale, CA 94086 408-481-2300 Contact Information This document contains information proprietary to Cortina Systems, Inc. Any use or disclosure, in whole or in part, of this information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as authorized by Cortina Systems, Inc. in writing. Cortina Systems, Inc. reserves its rights to pursue both civil and criminal penalties for copying or disclosure of this material without authorization. *Other names and brands may be claimed as the property of others. Cortina Systems, Inc. 2007 Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers End of Document Page 221 Cortina Systems, Inc. - Products keyword s SONET/SDH Ethernet RPR & ATM FEC/OTN PDH Telecom PON Digital Home Processors L X T 9 7 8 5 / 9 7 8 5 E - Low-Power 8-Port Ethernet Transceiver The LXT9785 and LXT9785E are Cortina's lowest power, highest performance octal 10/100 transceivers. The LXT9785/9785E transceivers simplify multi-port switch design through low power, previous-generation register compatibility, and multiple interfaces. The LXT9785/9785E transceiver complies with all applicable requirements of IEEE standards and demonstrates superior Ethernet performance with operation up to 200 meters. LXT9785 and LXT9785E are identical except for the Voice over IP VoIP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects data terminal equipment DTE capable of being powered remotely from the switch over a Category 5 cable. The system can use the information collected by the LXT9785E to apply power over the cable if the link partner requires it, such as an IP telephone. The LXT9785E offers an easy to use solution for OEMs designing VoIP systems that need to be as robust as typical PBX-based telephone systems. Ordering Information Click to see leaded to lead free designator codes Basename Order Code RoHS Status Media Type Package Leads End of Life LXT9785 WBLXT9785HE.D0-865114 RoHS 6 TRAY HQFP 208 No LXT9785 WBLXT9785HE.D0-865115 RoHS 6 HQFP 208 No LXT9785 WBLXT9785HC.D0-865112 RoHS 6 TRAY HQFP 208 No LXT9785 WBLXT9785HC.D0-865113 RoHS 6 HQFP 208 No LXT9785 WBLXT9785EHC.D0-865110 RoHS 6 TRAY HQFP 208 No LXT9785 WBLXT9785EHC.D0-865111 RoHS 6 HQFP 208 No LXT9785 PRLXT9785EBC.D0-865125 RoHS 6 TRAY PBGA 241 No LXT9785 PRLXT9785EBC.D0-865129 RoHS 6 PBGA 241 No

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Cortina LXT9785 and LXT9785E Advanced 8-Port 10/ 100 Mbps PHY Transceivers

Datasheet

The Cortina LXT9785 and LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces SMII/SS-SMII and Reduced Media Independent Interface RMII for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment DTE requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT9785E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone.

Each network port can provide a twisted-pair TP or Low-Voltage Positive Emitter Coupled Logic LVPECL interface. The twisted-pair interface supports 10 Mbps and 100 Mbps 10BASE-T and 100BASE-TX Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps 100BASE-FX Ethernet over fiber-optic media.

The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single V power supply.
- Enterprise switches - IP telephony switches

Product Features
- Storage Area Networks - Multi-port Network Interface Cards NICs
- Eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters.
- 100BASE-FX fiber-optic capability on all ports.
- V operation.
- Low power consumption 250 mW per port typical.
- Multiple RMII or SMII/SS-SMII ports for independent PHY port operation.
- Auto MDI/MDIX crossover capability.
- Proprietary Optimal Signal Processing architecture improves SNR by 3 dB over ideal analog filters.
- Optimized for dual-high stacked RJ-45 applications.
- MDIO sectionalization into 2x4 or 1x8 configurations.
- Supports both auto-negotiation systems and legacy systems without auto-negotiation capability.
- Robust baseline wander correction.
- Configurable through the MDIO port or external control pins.
- JTAG boundary scan.
- 208-pin PQFP LXT9785HC, LXT9785EHC, LXT9785HE.
- 241-ball BGA LXT9785BC, LXT9785EBC.
- 196-ball BGA LXT9785MBC includes DTE detection similar to the LXT9785E
- DTE detection for remote powering applications LXT9785E and LXT9785MBC only .
- Extended temperature operation of -40 oC to +85 oC LXT9785E only .

Contents

Contents

What You Will Find in This Document Related Documents

Block Diagram

Pin/Ball Assignments and Signal Descriptions

PQFP Pin Assignments PQFP Pin Assignments RMII Configuration PQFP Pin Assignments SMII PQFP Pin Assignments SS-SMII

PQFP Signal Descriptions Signal Name Conventions PQFP Signal Descriptions RMII, SMII, and SS-SMII Configurations..................36

BGA23 Ball RMII BGA23 Ball List SMII BGA23 Ball List SS-SMII BGA23 Ball List

BGA23 Signal Descriptions Signal Name Conventions Signal Descriptions RMII, SMII, and SS-SMII

BGA15 Ball BGA15 Ball

BGA15 Signal Descriptions Signal Name Conventions Signal Descriptions SMII and SS-SMII Configurations

Functional

Introduction OSP Architecture Comprehensive Functionality

Interface Descriptions 10/100 Network Twisted-Pair Interface MDI Crossover Fiber

Media Independent Interface MII Interfaces Global MII Mode Select Internal Loopback RMII Data Serial Media Independent Interface SMII and Source Synchronous- Serial Media Independent Interface SS-SMII Source Synchronous-Serial Media Independent Interface Configuration Management Interface MII Isolate MDIO Management Interface MII
Top Label Markings Ordering

Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

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Figures

Figures
1 Block Diagram 2 RMII 208-Pin PQFP Assignments 3 SMII 208-Pin PQFP Assignments 4 SS-SMII 208-Pin PQFP Assignments 5 241-Ball BGA23 Assignments Top View 6 196-Ball BGA15 Assignments Top View 7 Interface Signals 8 Internal Loopback 9 Management Interface Read Frame Structure 10 Management Interface Write Frame Structure 11 Port Address 12 Interrupt 13 Initialization 14 Auto-Negotiation Operation 15 Typical SMII 16 Typical SMII Quad Sectionalization 17 100 Mbps Serial MII Data Flow 18 Serial MII Transmit Synchronization 19 Serial MII Receive Synchronization 20 Typical SS-SMII 21 Typical SS-SMII Quad Sectionalization 22 SS-SMII Transmit Timing 23 SS-SMII Receive Timing 24 RMII Data 25 Typical RMII 26 Typical RMII Quad 27 100BASE-X Frame 28 Protocol Sublayers 29 Typical IP Telephone System 30 Cortina LXT9785E Negotiation Flow 31 LED Pulse Stretching 32 RMII Programmable Out-of-Band Signaling 33 LED Circuit 34 Power and Ground Supply Connections 35 Typical Twisted-Pair Interface 36 Recommended LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry...................167 37 Recommended LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry......................168 38 ON Semiconductor Triple PECL-to-LVPECL Translator 39 SMII - 100BASE-TX Receive Timing 40 SMII - 100BASE-TX Transmit Timing 41 SMII - 100BASE-FX Receive Timing 42 SMII - 100BASE-FX Transmit Timing 43 SMII - 10BASE-T Receive Timing 44 SMII - 10BASE-T Transmit Timing 45 SS-SMII - 100BASE-TX Receive Timing 46 SS-SMII - 100BASE-TX Transmit Timing 47 SS-SMII - 100BASE-FX Receive Timing 48 SS-SMII - 100BASE-FX Transmit Timing

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Figures
49 SS-SMII - 10BASE-T Receive Timing 50 SS-SMII - 10BASE-T Transmit Timing 51 RMII - 100BASE-TX Receive 52 RMII - 100BASE-TX Transmit 53 RMII - 100BASE-FX Receive 54 RMII - 100BASE-FX Transmit 55 RMII - 10BASE-T Receive Timing 56 RMII - 10BASE-T Transmit Timing 57 Auto-Negotiation and Fast Link Pulse Timing 58 Fast Link Pulse Timing 59 MDIO Write Timing MDIO Sourced by MAC 60 MDIO Read Timing MDIO Sourced by PHY 61 Power-Up 62 RESET_L Recovery 63 PHY Identifier Bit Mapping 64 208-Pin PQFP Plastic Package Specification 65 241-Ball BGA23 Package Specificationss - Top/Side Views 66 241-Ball BGA23 Package Specificationss - Bottom View LXT9785BC 67 196-Ball BGA15 Package Specs - Top/Side Views 68 196-Ball BGA15 Package Bottom View LXT9785MBC 69 Example of Top Marking Information Labeled as Cortina Systems, Inc. 70 Example of Top Marking Information Labeled as Intel Corporation* 71 Example of Top Marking Information Labeled as Level One Communications* 72 Ordering Information - Sample

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Tables

Tables
1 Signal Type Descriptions 2 RMII PQFP Pin List 3 SMII PQFP Pin 4 SS-SMII PQFP Pin 5 RMII Signal Descriptions PQFP 6 SMII/SS-SMII Common Signal Descriptions 7 SMII Specific Signal Descriptions PQFP 8 SS-SMII Specific Signal Descriptions PQFP 9 MDIO Control Interface Signals PQFP 10 Signal Detect PQFP 11 Network Interface Signal Descriptions PQFP 12 JTAG Test Signal Descriptions PQFP 13 Miscellaneous Signal Descriptions PQFP 14 LED Signal Descriptions PQFP 15 Power Supply Signal Descriptions PQFP 16 Unused/Reserved Pins PQFP 17 Receive FIFO Depth Considerations 18 RMII BGA23 Ball List in Alphanumeric Order by Signal Name 19 RMII BGA23 Ball List in Alphanumeric Order by Ball Location 20 SMII BGA23 Ball List in Alphanumeric Order by Signal 21 SMII BGA23 Ball List in Alphanumeric Order by Ball 22 SS-SMII BGA23 Ball List in Alphanumeric Order by Signal 23 SS-SMII BGA23 Ball List in Alphanumeric Order by Ball 24 RMII Signal Descriptions 25 SMII/SS-SMII Common Signal Descriptions BGA23 26 SMII Specific Signal Descriptions BGA23 27 SS-SMII Specific Signal Descriptions BGA23 28 MDIO Control Interface Signals BGA23 29 Signal Detect 30 Network Interface Signal Descriptions BGA23 31 JTAG Test Signal Descriptions BGA23 32 Miscellaneous Signal Descriptions BGA23 33 LED Signal Descriptions BGA23 34 Power Supply Signal Descriptions BGA23 35 Unused/Reserved Pins BGA23 36 Receive FIFO Depth 37 LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name 38 LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location SMII/SS-SMII 39 BGA15 Signal Descriptions 40 MDIX Selection 41 MII Mode 42 Global Hardware Configuration Settings 43 SMII Signal Summary 44 RX Status Encoding Bit Definitions 45 SS-SMII 46 4B/5B Coding 47 DTE Terms 48 Next Page Message #5 Code Word Definitions

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Tables
49 BSR Mode of Operation 50 Supported JTAG Instructions 51 Magnetics Requirements 52 Absolute Maximum Ratings 53 Operating Conditions 54 Digital I/O DC Electrical Characteristics VCCIO = V +/- 5% 55 Digital I/O DC Electrical Characteristics VCCIO = V +/- 5% 56 Digital I/O DC Electrical Characteristics SD Pins 57 Required Clock Characteristics 58 100BASE-TX Transceiver 59 100BASE-FX Transceiver 60 10BASE-T Transceiver Characteristics 61 SMII - 100BASE-TX Receive Timing Parameters 62 SMII - 100BASE-TX Transmit Timing Parameters 63 SMII - 100BASE-FX Receive Timing Parameters 64 SMII - 100BASE-FX Transmit Timing Parameters 65 SMII - 10BASE-T Receive Timing 66 SMII-10BASE-T Transmit Timing 67 SS-SMII - 100BASE-TX Receive Timing Parameters 68 SS-SMII - 100BASE-TX Transmit Timing 69 SS-SMII - 100BASE-FX Receive Timing Parameters 70 SS-SMII - 100BASE-FX Transmit Timing Parameters 71 SS-SMII - 10BASE-T Receive Timing 72 SS-SMII - 10BASE-T Transmit Timing 73 RMII - 100BASE-TX Receive Timing Parameters 74 RMII - 100BASE-TX Transmit Timing Parameters 75 RMII - 100BASE-FX Receive Timing Parameters 76 RMII - 100BASE-FX Transmit Timing Parameters 77 RMII - 10BASE-T Receive Timing Parameters 78 RMII - 10BASE-T Transmit Timing Parameters 79 Auto-Negotiation and Fast Link Pulse Timing Parameters 80 MDIO Timing Parameters 81 Power-Up Timing Parameters 82 RESET_L Recovery Timing Parameters 83 Register 84 Control Register Address 0 85 Status Register Address 1 86 PHY Identification Register 1 Address 2 87 PHY Identification Register 2 Address 3 88 Auto-Negotiation Advertisement Register Address 4 89 Auto-Negotiation Link Partner Base Page Ability Register Address 5 90 Auto-Negotiation Expansion Register Address 6 91 Auto-Negotiation Next Page Transmit Register Address 7 92 Auto-Negotiation Link Partner Next Page Receive Register Address 93 Port Configuration Register Address 16, Hex 10 94 Quick Status Register Address 17, Hex 11 95 Interrupt Enable Register Address 18, Hex 96 Interrupt Status Register Address 19, Hex 97 LED Configuration Register Address 20, Hex 14 98 Receive Error Count Register Address 21, Hex

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Tables
99 RMII Out-of-Band Signaling Register Address 25, Hex 19 100 Trim Enable Register Address 27, Hex 1B 101 Cable Diagnostics Register Address 29, Hex 102 Register Bit Map 103 241-Ball BGA23 Package Dimensions 104 196-Ball BGA15 Package Dimensions LXT9785MBC 105 Product Information

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Page 48 page 93 page 123
page 126
page 192 page 195 page 200 page 217
page 219
Modified signal description text for VCCPECL in Table 15, Power Supply Signal Descriptions PQFP. Modified signal description text for VCCPECL in Table 34, Power Supply Signal Descriptions BGA23. Added note under Section RxCLK Signal SS-SMII Only . Modified CFG 1,2,3 settings for Register bit when set to “1” in Table 42, Global Hardware Configuration Settings. Added table note 6 to Register bit Loopback in Table 84, Control Register Address 0 Modified table note 6 for Register bit in Table 88, Auto-Negotiation Advertisement Register Address Modified note in Register bit Collision Status in Table 94, Quick Status Register Address 17, Hex Added Section Top Label Markings. Modified Section Ordering Information Table 105, Product Information and Figure 72, Ordering Information Sample.

Page 1 43 88 53
229 230
Modified 196-Ball BGA and DTE Detection bullets under Product Features. Added table note 3 regarding LINKHOLD to Table 13, Miscellaneous Signal Descriptions PQFP, on page Added table note 3 regarding LINKHOLD to Table 32, Miscellaneous Signal Descriptions BGA23, on page Modified Table 18 “RMII BGA23 Ball List in Alphanumeric Order by Signal Name” through Table 23 “SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location” for ball, type, and reference page corrections. Modified Table 104 “Product Information” [added new packaging information]. Modified Figure 69 “Ordering Information - Sample” [changed Internal Package Designator for B and E, and added the GD and definition under Package Designator .

Page All 229

Globally added LEDn_3 to BGA15. Added Figure 68 “Cortina LXT9785MBC 196-Ball BGA15 Package Bottom View”.

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21 22 26 27 31 32 36 40 43 50 51
82 86 90 97
116 117 119 120 121

Modified Figure 2 “Cortina LXT9785 and Cortina LXT9785E RMII 208-Pin PQFP Assignments”. Modified Table 2 “Cortina LXT9785/LXT9785E RMII PQFP Pin List”. Modified Figure 3 “Cortina LXT9785/LXT9785E SMII 208-Pin PQFP Assignments”. Modified Table 3 “Cortina LXT9785/LXT9785E SMII PQFP Pin List”. Modified Figure 4 “Cortina LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments”. Modified Table 4 “Cortina LXT9785/LXT9785 SS-SMII PQFP Pin List”. Modified Table 5 “Cortina LXT9785/LXT9785E RMII Signal Descriptions PQFP”. Modified Table 8 “Cortina LXT9785/LXT9785E SS-SMII Specific Signal Descriptions PQFP”. Modified Table 13 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions PQFP”. Modified Table 16 “Cortina LXT9785/LXT9785E Unused/Reserved Pins PQFP”. Replaced old Figures 5, 6, and 7 with Figure 5 “Cortina LXT9785/LXT9785E 241-Ball BGA23 Assignments Top View ”. Modified Table 18 “Cortina LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name”. Modified Table 19 “Cortina LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location”. Modified Table 20 “Cortina LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name”. Modified Table 21 “Cortina LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location” Modified Table 22 “Cortina LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name”. Modified Table 23 “Cortina LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location”. Modified Table 23 “Cortina LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location”. Modified Table 27 “Cortina LXT9785/LXT9785E SS-SMII Specific Signal Descriptions BGA23”. Modified Table 32 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions BGA23”. Modified Table 35 “Cortina LXT9785/LXT9785E Unused/Reserved Pins BGA23”. Added Section “BGA15 Ball Assignments” including Figure 6 “Cortina LXT9785MBC 196-Ball BGA15 Assignments Top View ”, Table 37 “Cortina LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” through Table 39 “Cortina LXT9785 BGA15 Signal Descriptions”.

Added second paragraph under Section “Introduction”.

Added note under Section “Sectionalization”. Added note under Table 40 “Cortina LXT9785/LXT9785E MDIX Selection”.

Added note under Section “Media Independent Interface MII Interfaces”. Added note to Table 41 “Cortina LXT9785/LXT9785E MII Mode Select”.

Modified/added text under Section “Internal Loopback”.

Modified text under Section “MII Isolate”.

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123 124 125 127 128 129 130
131 136 141 148 149 150 151 152 153 154 155 157 158 160 161 162 173 176

Section “MDIO Management Interface” Added note under second paragraph. Added last paragraph. Added note under Section “MII Sectionalization”. Added new Section “FIFO Initial Fill Values” Modified paragraph three under Section “Power Requirements”. Added notes under second and last paragraphs under Section “Power-Down Mode”. Modified last bullet under Section “Global Hardware Power Down”. Added last paragraph to Section “Reset”. Modified Table 42 “Cortina LXT9785/LXT9785E Global Hardware Configuration Settings”. Change heading and modified last line under Section “Manual Next Page Exchange”. Section “Link Criteria” Changed scrambler to descrambler in first line. Modified second paragraph. Added two new paragraphs. Added second paragraph under Section “Parallel Detection”. Modified paragraphs under Section “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode”. Changed “1110” to “0101” under Section “Receive Error”. Added note under first paragraph of Section “RMII Operation” Changed “asynchronously” to “synchronously” in second paragraph under Section “Carrier Sense/Data Valid RMII ”. Modified last sentence in first paragraph under Section “Carrier Sense SMII ”. Modified paragraph under Section “Polarity Correction”. Added note under Section “Fiber PMD Sublayer”. Added second paragraph under Section “Far End Fault Indications”. Modified/added text under Section “Preamble Handling”. Modified text under Section “Jabber”. Modified first paragraph under Section “DTE Discovery Process”. Modified Item 1 of Section “Interaction between Processor, MAC, and PHY”. Modified second paragraph under Section “DTE Discovery Process Flow”. Added Section “DTE Discovery Behavior” Added BGA15 information into first paragraph under Section “Per-Port LED Driver Functions”. Added last sentence to first paragraph and note under first paragraph under Section “Out-of-Band Signaling”. Added Section “Cable Diagnostics Overview”. Modified/added text under Section “Implementation Considerations”. Added Section “Link Hold-Off Overview”. Modified Table 52 “Cortina LXT9785/LXT9785E Operating Conditions” Modified Table 58 “Cortina LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”

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178-195
199 200 201 203 204 205 206 207 209 211 212 213 214 215 216 217 219 226 227
Description Added note to Table 60 “Cortina LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters” through Table 77 “Cortina LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters”. Added table note to Table 60 “Cortina LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters”. Added table note to Table 66 “Cortina LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters”. Added table note to Table 72 “Cortina LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters” Added software power-down and note to Table 80 “Cortina LXT9785/LXT9785E Power-Up Timing Parameters”. Modified paragraphs and added last paragraph under Section “Register Definitions”. Modified Table 82 “Cortina LXT9785/LXT9785E Register Set”. Modified Table 83 “Control Register Address Modified Table 84 “Status Register Address Modified Table 85 “PHY Identification Register 1 Address Modified Table 86 “PHY Identification Register 2 Address 3 ” Modified Table 87 “Auto-Negotiation Advertisement Register Address 4 ” Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register Address Modified Table 89 “Auto-Negotiation Expansion Register Address Modified Table 90 “Auto-Negotiation Next Page Transmit Register Address Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register Address Modified Table 92 “Port Configuration Register Address 16, Hex Register bits Modified Table 93 “Quick Status Register Address 17, Hex Register bit Modified Table 94 “Interrupt Enable Register Address 18, Hex 12 ” Modified Table 95 “Interrupt Status Register Address 19, Hex 13 ” Modified Table 96 “LED Configuration Register Address 20, Hex 14 ” Modified Table 97 “Receive Error Count Register Address 21, Hex Modified Table 98 “RMII Out-of-Band Signaling Register Address 25, Hex Modified Table 99 “Trim Enable Register Address 27, Hex 1B ”. Register bit Added Table 100 “Cable Diagnostics Register Address 29, Hex 1D ”. Modified Table 101 “Cortina LXT9785/LXT9785E Register Bit Map”. Added Figure 102 “Cortina LXT9785MBC 196-Ball BGA15 Package Dimensions” Modified table and figure under Section “Ordering Information”.

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36 42 43
116 119 120 130 131 136 145 146 148 149 150 151 152 153 158 166 170
171 173 174
175 176

Changed "pseudo-ECL PECL " to "Low Voltage Positive Emitter Coupled Logic LVPECL " in the second paragraph, front page. Modified Table 5 “Cortina LXT9785/LXT9785E RMII Signal Descriptions PQFP”. Added last sentence to RXER0 through RXER7 signal description. Modified Table 10 “Cortina LXT9785/LXT9785E Signal Detect PQFP”. Modified Table 11 “Cortina LXT9785/LXT9785E Network Interface Signal Descriptions PQFP”, Modified Table 13 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions PQFP”. Added note to PREASEL signal description.

Modified Section “Introduction”. Changed "Pseudo-ECL PECL " to "Low Voltage PECL LVPECL " in the first paragraph, second sentence.

Replace text under Section “Fiber Interface”.

Modified Section “Internal Loopback”.

Modified last sentence under Section “Link Criteria”.

Modified text under Section “Parallel Detection”. Added second paragraph.

Modified text under Section “Receive Error”.

Changed "PECL" to "LVPECL in third paragraph, first sentence under Section “100BASE-X Network Operations”. Modified Figure 28 “Cortina LXT9785/LXT9785E Protocol Sublayers”.

Modified Section “Carrier Sense/Data Valid RMII ”. Changed “asynchronously to “synchronously.”

Modified paragraph under Section “Polarity Correction”.

Replaced text under Section “Fiber PMD Sublayer”.

Modified Section “Preamble Handling”. Added text to last paragraph.

Modified first sentence under Section “Jabber”.

Modified first paragraph of Section “DTE Discovery Process”.

Modified Item 1 of Section “Interaction between Processor, MAC, and PHY”.

Modified Section “Out-of-Band Signaling”. Added sentence to end of first paragraph.

Replaced text under Section “The Fiber Interface”. Replaced Figure 36 “Recommended Cortina LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry”. Replaced Figure 37 “Recommended Cortina LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry”. Modified Table 52 “Cortina LXT9785/LXT9785E Operating Conditions”. Modified Table 53 “Cortina LXT9785/LXT9785E Digital I/O DC Electrical Characteristics VCCIO = V +/- Modified Table 54 “Cortina LXT9785/LXT9785E Digital I/O DC Electrical Characteristics VCCIO = V +/- Added Table 55 “Cortina LXT9785/LXT9785E Digital I/O DC Electrical Characteristics SD Pins”. Modified Table 58 “Cortina LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics”.

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Page 200 201 204 205 207 209 211 212 214 215 216 227

Description Modified Table 83 “Control Register Address Modified Table 84 “Status Register Address Modified Table 87 “Auto-Negotiation Advertisement Register Address Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register Address Modified Table 91 “Auto-Negotiation Link Partner Next Page Receive Register Address Modified Table 92 “Port Configuration Register Address 16, Hex Modified Table 93 “Quick Status Register Address 17, Hex Modified Table 94 “Interrupt Enable Register Address 18, Hex 12 ” Modified Table 95 “Interrupt Status Register Address 19, Hex Changed all references of RO/SC to R/LH. Modified Table 97 “Receive Error Count Register Address 21, Hex Modified Table 98 “RMII Out-of-Band Signaling Register Address 25, Hex Added note to Register bit Modified Table 99 “Trim Enable Register Address 27, Hex 1B ”. Modified Table 103 “Product Information”.

Page 1 49 70
110 111 112 114

Added bullet to Product Features Modified Table 12 “Cortina LXT9785/LXT9785E Miscellaneous Signal Descriptions” Added FIFOSEL1 and FIFOSEL0

Added Section “Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode” Modified Figure 38 “Recommended Cortina LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry” Added Figure 39 “Recommended Cortina LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry”

Added Figure 40 “ON Semiconductor Triple PECL-to-LVPECL Translator”

Modified Table 28 “Absolute Maximum Ratings”

Modified Table 29 “Operating Conditions”

Modified Table 31 “Digital I/O DC Electrical Characteristics VCCIO = V +/- 5% ” Output low voltage SD pins Max

Modified Figure 53 “RMII - 100BASE-TX Receive Timing” and Table 49 “RMII - 100BASE-TX Receive Timing Parameters”

Modified Figure 55 “RMII - 100BASE-FX Receive Timing” and Table 51 “RMII - 100BASE-FX Receive Timing Parameters”

Modified Figure 57 “RMII - 10BASE-T Receive Timing” and Table 53 “RMII - 10BASE-T Receive Timing Parameters”

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Description Modified Table 69 “Port Configuration Register Address 16, Hex 10 ” Bits and Modified Table 71 “Interrupt Enable Register Address 18, Hex 12 ” Added product ordering table and diagram.

Page 1 61 85 93 97 99
102 122 126 128 131 133 140 141

Description Modified and added new language to front page. Reset Modified language in first paragraph. Added new section on DTE discovery. Supported JTAG Instructions table replaced long hit streams with hex. LED Circuit Modified paragraph language. LED Circuit diagram Modified diagram. Replaced Typical Fiber Interface diagram. Required Clock Characteristics table Replaced SMII Input frequency and RMII Input frequency symbol with “f”. Auto-Negotiation and Fast Link Pulse Timing Parameters FLP burst width under Typ = Control Register table Modified table and table notes. PHY Identification Register 2 Address 3 Modified table. PHY Identifier Bit Mapping Modified diagram. Auto-Negotiation Expansion Modified table and table notes. Port Configuration Register table Modified table and table notes. Trim Enable Register Modified table DTE Discovery . Modified Register Bit Map table.

Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Page 17

Introduction

Introduction

This document contains information on the Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers.

What You Will Find in This Document
This document contains the following sections
• Section Block Diagram, on page 19
• Section Pin/Ball Assignments and Signal Descriptions, on page 20 This section contains pin/ball assignments and signal descriptions for the following Section PQFP Pin Assignments, on page 20 Section PQFP Signal Descriptions, on page 36 Section BGA23 Ball Assignments, on page 51 Section BGA23 Signal Descriptions, on page 79 Section BGA15 Ball Assignments, on page 97 Section BGA15 Signal Descriptions, on page 106
• Section Functional Description, on page 113
• Section Application Information, on page 161
• Section Test Specifications, on page 170
• Section Register Definitions, on page 191
• Section Package Specifications, on page 212
• Section Ordering Information, on page 219

Related Documents

Document

Cortina LXT9785/LXT9785E Design and Layout Guide Cortina LXT9785/LXT9785E Specification Update Cortina LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers Connecting a PECL/LVPECL Interface IP Telephony and DTE Discovery Using Cortina Ethernet PHYs

Document Number 249509 249357
250781
249611

Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Page 18

Block Diagram

Figure 1

Block Diagram

Figure 1 provides the LXT9785/LXT9785E block diagram. Block Diagram

RMII/SMII Contr

ADD_[4:0]

MDIO

MDC 2

MDINT_L 2

TxDatan

LEDn_[3:1]_L

RxDatan

RX PCS

Management / Mode Select Logic & LED

Drivers
8-Port Global Functions

Clock Generator

TX PCS

Mgmt Counters

Register Set

Register Set

Parallel/Serial Converter

Manchester Encoder 10

Scrambler 100 & Encoder

Pulse Shaper

Auto Negotiation

TP Driver

ECL Driver

TP / Fiber Out

Port LED Drivers

Clock Generator

Media Select
Ordering Information
Ordering Information
Table 105 and Figure 72 provide product ordering information.

Table 105

Product Information

Number FWLXT9785BC.D0 PRLXT9785BC.D0 FWLXT9785EBC.D0 PRLXT9785EBC.D0 FWLXT9785BC.C2V PRLXT9785BC.C2V FWLXT9785EBC.C2V PRLXT9785EBC.C2V GDLXT9785MBC.D0 LULXT9785MBC.D0 HBLXT9785HC.D0 WBLXT9785HC.D0 HBLXT9785EHC.D0 WBLXT9785EHC.D0 HBLXT9785HE.D0 WBLXT9785HE.D0 HBLXT9785EHC.C2V WBLXT9785EHC.C2V HBLXT9785HC.C2V WBLXT9785HC.C2V HBLXT9785HE.C2V WBLXT9785HE.C2V

Package Type PBGA HQFP

Pin Count 241 196 208

RoHS Compliant No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes

Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Page 219
Ordering Information
Figure 72 Ordering Information - Sample FW LXT 9785E B C A6 S E001

Build Format E000 =Tray E001 = Tape and reel

Qualification Q =Pre-production material S = Production material

Temperature Range A = Ambient 0 - 55° C =Commercial 0 - 70° C E = Extended -40 - +85° C

Internal Package Designator L = LQFP P = PLCC N = DIP Q = PQFP H = QFP with heat spreader T = TQFP B =BGA E = TBGA K = HSBGA BGA with heat slug
xxxx = 3-5 Digit Alphanumeric Product Code

Product Prefix LXT =PHYlayer device IXF = Formatting device MAC

Package Designator DJ = LQFP FA = TQFP FL = PBGA mm pitch FW =PBGA 1.27mmpitch HB =QFPwithheat spreader HD = QFP with heat slug HG =SOIC S =QFP GC =TBGA N = PLCC

LXT9785 = Nominal device LXT9785E = DTE detection feature LXT9785MBC = 196 ball BGA with DTE detection feature

Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Page 220

Contact Information

Cortina Systems, Inc. 840 W. California Ave Sunnyvale, CA 94086 408-481-2300

Contact Information

This document contains information proprietary to Cortina Systems, Inc. Any use or disclosure, in whole or in part, of this information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as authorized by Cortina Systems, Inc. in writing. Cortina Systems, Inc. reserves its rights to pursue both civil and criminal penalties for copying or disclosure of this material without authorization. *Other names and brands may be claimed as the property of others.

Cortina Systems, Inc. 2007

Cortina LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

End of Document

Page 221

Cortina Systems, Inc. - Products
keyword s

SONET/SDH Ethernet RPR & ATM FEC/OTN PDH Telecom PON Digital Home Processors

L X T 9 7 8 5 / 9 7 8 5 E - Low-Power 8-Port Ethernet Transceiver

The LXT9785 and LXT9785E are Cortina's lowest power, highest performance octal 10/100 transceivers. The LXT9785/9785E transceivers simplify multi-port switch design through low power, previous-generation register compatibility, and multiple interfaces. The LXT9785/9785E transceiver complies with all applicable requirements of IEEE standards and demonstrates superior Ethernet performance with operation up to 200 meters. LXT9785 and LXT9785E are identical except for the Voice over IP VoIP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects data terminal equipment DTE capable of being powered remotely from the switch over a Category 5 cable. The system can use the information collected by the LXT9785E to apply power over the cable if the link partner requires it, such as an IP telephone. The LXT9785E offers an easy to use solution for OEMs designing VoIP systems that need to be as robust as typical PBX-based telephone systems.
Ordering Information

Click to see leaded to lead free designator codes

Basename

Order Code

RoHS Status Media Type Package Leads End of Life

LXT9785

WBLXT9785HE.D0-865114 RoHS 6

TRAY

HQFP
208 No

LXT9785

WBLXT9785HE.D0-865115 RoHS 6

HQFP
208 No

LXT9785

WBLXT9785HC.D0-865112 RoHS 6

TRAY

HQFP
208 No

LXT9785

WBLXT9785HC.D0-865113 RoHS 6

HQFP
208 No

LXT9785

WBLXT9785EHC.D0-865110 RoHS 6

TRAY

HQFP
208 No

LXT9785

WBLXT9785EHC.D0-865111 RoHS 6

HQFP
208 No

LXT9785

PRLXT9785EBC.D0-865125 RoHS 6

TRAY

PBGA
241 No

LXT9785

PRLXT9785EBC.D0-865129 RoHS 6

PBGA
241 No

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived QWLXT9785BC.D0-998807 Datasheet file may be downloaded here without warranties.

Datasheet ID: QWLXT9785BC.D0-998807 506897