5962-9459903MXA

5962-9459903MXA Datasheet

STK12C68-5 SMD5962-94599

Part	Datasheet
5962-9459903MXA	5962-9459903MXA (pdf)

Related Parts	Information
5962-9459903MYA	5962-9459903MYA
5962-9459901MXA	5962-9459901MXA

PDF Datasheet Preview
STK12C68-5 SMD5962-94599 64 Kbit 8 K x 8 AutoStore nvSRAM • 35 ns and 55 ns access times • Hands off automatic STORE on power down with external 68 µF capacitor • STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power down • RECALL to SRAM initiated by software or power up • Unlimited Read, Write, and Recall cycles • 1,000,000 STORE cycles to QuantumTrap • 100 year data retention to QuantumTrap • Single 5 V + 10% operation • Military temperature • 28-pin 300mil CDIP and 28-pad LCC packages Functional Description The Cypress STK12C68-5 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down. On power up, data is restored to the SRAM the RECALL operation from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. For a complete list of related documentation, click here. Logic Block Diagram A5 A6 A7 A8 A9 A 11 A 12 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 INPUT BUFFERS ROW DECODER Quantum Trap 128 X 512 STORE STATIC RAM ARRAY 128 X 512 RECALL COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 VCAP POWER CONTROL STORE/ RECALL CONTROL SOFTWARE DETECT - A0 A12 CE WE • San Jose, CA 95134-1709 • 408-943-2600 STK12C68-5 SMD5962-94599 Contents Pinouts 3 Pin Definitions 3 Device Operation 4 SRAM Read 4 SRAM Write 4 AutoStore Operation 4 AutoStore Inhibit Mode 5 Hardware STORE HSB 5 Hardware RECALL Power 5 Software STORE 5 Software 5 Data Protection 6 Noise 6 Hardware 6 Low Average Active 6 Preventing 6 Best 7 Maximum 8 Operating Range 8 DC Electrical Characteristics 8 Data Retention and Endurance 9 Capacitance 9 Thermal 9 AC Test Conditions 9 SRAM Read Cycle 10 SRAM Write 11 AutoStore or Power Up RECALL 12 Software Controlled STORE/RECALL Cycle................ 13 Switching Waveform 14 Part Numbering 15 Ordering 16 Acronyms 17 Document Conventions 17 Units of Measure 17 Document History Page 18 Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support....................... 18 Products 18 PSoC Solutions 18 Page 2 of 18 STK12C68-5 SMD5962-94599 Pinouts Figure Pin Diagram - 28-Pin CDIP VCAP A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VCC WE HSB A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Figure Pin Diagram - 28-Pin LCC Pin Definitions Pin Name Alt IO Type DQ0-DQ7 Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. VSS VCC Ground for the Device. The device is connected to ground of the system. Power Supply Power Supply Inputs to the Device. Input or Output Hardware Store Busy HSB . When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected connection optional . VCAP Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. Page 3 of 18 STK12C68-5 SMD5962-94599 Device Operation The STK12C68-5 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation . This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK12C68-5 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. SRAM Read The STK12C68-5 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins determines the 8,192 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA Read cycle If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later Read cycle The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins are written into the memory if it has valid tSD, before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation The STK12C68-5 stores data to nvSRAM using one of three storage operations Hardware store activated by HSB Software store activated by an address sequence AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK12C68-5. Ordering Information Speed ns Ordering Code Package Diagram Package Type STK12C68-5C35M 001-51695 28-pin CDIP 300 mil STK12C68-5L35M 001-51696 28-pin LCC 350 mil STK12C68-5C55M 001-51695 28-pin CDIP 300 mil STK12C68-5L55M 001-51696 28-pin LCC 350 mil The above table contains Final information. Contact your local Cypress sales representative for availability of these parts Package Diagrams Figure 28-Pin 300-Mil Side Braze DIP 001-51695 Operating Range Military 001-51695 C Page 16 of 18 STK12C68-5 SMD5962-94599 Package Diagrams continued Figure 28-Pad 350-Mil LCC 001-51696 Acronyms Acronym CE CMOS I/O nvSRAM OE SRAM TTL WE Description chip enable complementary metal oxide semiconductor input/output nonvolatile static random access memory output enable static random access memory transistor-transistor logic write enable 001-51696 C Document Conventions Units of Measure Symbol °C mA ms ns pF V Unit of Measure degrees Celsius kilohm microampere milliampere microfarad microsecond millisecond nanosecond picofarad volt ohm watt Page 17 of 18 STK12C68-5 SMD5962-94599 Document History Page Document Title STK12C68-5 SMD5962-94599 , 64 Kbit 8 K x 8 AutoStore nvSRAM Document Number 001-51026 Orig. of Change Submission Date Description of Change 2666844 GVCH/PYRS 03/02/09 New datasheet 3528539

PDF Datasheet Preview

STK12C68-5 SMD5962-94599
64 Kbit 8 K x 8 AutoStore nvSRAM
• 35 ns and 55 ns access times
• Hands off automatic STORE on power down with external
68 µF capacitor
• STORE to QuantumTrap nonvolatile elements is initiated
by software, hardware, or AutoStore on power down
• RECALL to SRAM initiated by software or power up
• Unlimited Read, Write, and Recall cycles
• 1,000,000 STORE cycles to QuantumTrap
• 100 year data retention to QuantumTrap
• Single 5 V + 10% operation
• Military temperature
• 28-pin 300mil CDIP and 28-pad LCC packages

Functional Description

The Cypress STK12C68-5 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down. On power up, data is restored to the SRAM the RECALL operation from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin. For a complete list of related documentation, click here.

Logic Block Diagram

A5 A6 A7 A8 A9 A 11 A 12

DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7

INPUT BUFFERS

ROW DECODER

Quantum Trap 128 X 512

STORE

STATIC RAM ARRAY 128 X 512

RECALL

COLUMN I/O COLUMN DEC

A0 A1 A2 A3 A4 A10

VCAP

POWER CONTROL

STORE/ RECALL CONTROL

SOFTWARE DETECT
- A0 A12

CE WE
• San Jose, CA 95134-1709
• 408-943-2600

STK12C68-5 SMD5962-94599

Contents

Pinouts 3 Pin Definitions 3 Device Operation 4 SRAM Read 4 SRAM Write 4 AutoStore Operation 4 AutoStore Inhibit Mode 5 Hardware STORE HSB 5 Hardware RECALL Power 5 Software STORE 5 Software 5 Data Protection 6 Noise 6 Hardware 6 Low Average Active 6 Preventing 6 Best 7 Maximum 8 Operating Range 8 DC Electrical Characteristics 8

Data Retention and Endurance 9 Capacitance 9 Thermal 9 AC Test Conditions 9
SRAM Read Cycle 10 SRAM Write 11 AutoStore or Power Up RECALL 12 Software Controlled STORE/RECALL Cycle................ 13 Switching Waveform 14 Part Numbering 15 Ordering 16 Acronyms 17 Document Conventions 17 Units of Measure 17 Document History Page 18 Sales, Solutions, and Legal Information 18 Worldwide Sales and Design Support....................... 18 Products 18 PSoC Solutions 18

Page 2 of 18

STK12C68-5 SMD5962-94599

Pinouts

Figure Pin Diagram - 28-Pin CDIP

VCAP A12 A7 A6 A5 A4

A3 A2

A1 A0 DQ0 DQ1 DQ2

VCC WE HSB

A8 A9 A11 OE A10 CE DQ7

DQ6 DQ5 DQ4 DQ3

Figure Pin Diagram - 28-Pin LCC

Pin Definitions

Pin Name Alt

IO Type

DQ0-DQ7

Input

Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input

Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.

VSS VCC

Ground for the Device. The device is connected to ground of the system. Power Supply Power Supply Inputs to the Device. Input or Output Hardware Store Busy HSB . When LOW, this output indicates a Hardware Store is in
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected connection optional .

VCAP

Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements.

Page 3 of 18

STK12C68-5 SMD5962-94599

Device Operation

The STK12C68-5 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation . This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK12C68-5 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations.

SRAM Read

The STK12C68-5 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins determines the 8,192 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA Read cycle If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later Read cycle The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.

SRAM Write

A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins are written into the memory if it has valid tSD, before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.

AutoStore Operation

The STK12C68-5 stores data to nvSRAM using one of three storage operations Hardware store activated by HSB Software store activated by an address sequence AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK12C68-5.
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type

STK12C68-5C35M
001-51695
28-pin CDIP 300 mil

STK12C68-5L35M
001-51696
28-pin LCC 350 mil

STK12C68-5C55M
001-51695
28-pin CDIP 300 mil

STK12C68-5L55M
001-51696
28-pin LCC 350 mil

The above table contains Final information. Contact your local Cypress sales representative for availability of these parts

Package Diagrams

Figure 28-Pin 300-Mil Side Braze DIP 001-51695

Operating Range Military
001-51695 *C

Page 16 of 18

STK12C68-5 SMD5962-94599

Package Diagrams continued

Figure 28-Pad 350-Mil LCC 001-51696

Acronyms

Acronym CE CMOS I/O nvSRAM OE SRAM TTL WE

Description chip enable complementary metal oxide semiconductor input/output nonvolatile static random access memory output enable static random access memory transistor-transistor logic write enable
001-51696 *C

Document Conventions

Units of Measure

Symbol °C mA ms ns pF V

Unit of Measure degrees Celsius kilohm microampere milliampere microfarad microsecond millisecond nanosecond picofarad volt ohm watt

Page 17 of 18

STK12C68-5 SMD5962-94599

Document History Page

Document Title STK12C68-5 SMD5962-94599 , 64 Kbit 8 K x 8 AutoStore nvSRAM Document Number 001-51026

Orig. of Change

Submission Date

Description of Change
2666844 GVCH/PYRS 03/02/09 New datasheet
3528539

More datasheets: 891626 BK013 | 891626 BK010 | 891626 YL013 | 891626 WH013 | 891626 GR013 | 891626 VI013 | DFR0060 | VPC-12 | VPC-10A | 5962-9459903MYA

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Datasheet ID: 5962-9459903MXA 508334