EGLXT973QEA3V-873108

EGLXT973QEA3V-873108 Datasheet

SLXT973QC Transceiver EGLXT973QC Transceiver RoHS Compliant

Part	Datasheet
EGLXT973QEA3V-873108	EGLXT973QEA3V-873108 (pdf)

Related Parts	Information
EGLXT973QEA3V-873181	EGLXT973QEA3V-873181
EGLXT973QCA3V-873178	EGLXT973QCA3V-873178
EGLXT973QCA3V-873168	EGLXT973QCA3V-873168

PDF Datasheet Preview
Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Datasheet The Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver LXT973 Transceiver is an IEEE compliant, dual-port, Fast Ethernet PHY transceiver that directly supports both 100BASE-TX and 10BASE-T applications. Each port provides a Media Independent Interface MII for easy attachment to 10 Mbps and 100 Mbps Media Access Controllers MACs . The LXT973 Transceiver also provides a Low-Voltage Positive Emitter Coupled Logic LVPECL interface per port for use with 100BASE-FX fiber networks. The LXT973 Transceiver incorporates the auto MDI/MDIX feature, allowing it to automatically switch twisted-pair inputs and outputs. The LXT973 Transceiver is an ideal building block for systems that require two Ethernet ports, such as Internet Protocol IP Telephones, Twisted-Pair TX -to-Fiber FX converter modules, and for telecom applications, such as Telecom Central Office TCO and Customer Premise Equipment CPE devices. The LXT973 Transceiver supports full-duplex operation at both 10 Mbps and 100 Mbps. Its operating modes can be set using auto-negotiation, parallel detection, or manual control. Enterprise switches IP telephony switches Storage Area Networks Multi-port Network Interface Cards NICs Product Features Dual-port Fast Ethernet PHY 20 MHz Register Access Voperation I/O compatibility Low power consumption 250 mW per port typical Configurable via MDIO port or external control pins Integrated termination resistors 100-pin Plastic Quad Flat Package PQFP Full dual-port MII interface with extended registers Auto MDI/MDIX switch over capability • Commercial 0 C to 70 C ambient SLXT973QC Transceiver EGLXT973QC Transceiver RoHS Compliant Signal Quality Error SQE enable/disable 100BASE-FX fiber-optic capability on both ports Supports both auto-negotiation systems and legacy systems without auto-negotiation capability • -40 C to +85 C ambient Extended SLXT973QE Transceiver EGLXT973QE Transceiver RoHS Compliant Support for Next Page Legal Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. CORTINA , and the Cortina Earth Logo are trademarks or registered trademarks of Cortina Systems, Inc. or its subsidiaries in the US and other countries. Any other product and company names are the trademarks of their respective owners. Copyright Cortina Systems, Inc. All rights reserved. Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Contents Contents Pin Assignments and Signal Descriptions 14 Signal Descriptions 18 Functional 24 Introduction 24 Comprehensive Functionality 24 Interface Descriptions 24 10/100 Mbps Network 24 Twisted-Pair Interface 25 MDI Crossover 26 Fiber 26 MII Operation 26 MII Clocks 26 Transmit 26 Receive Data Valid 26 Carrier 27 Error Signals 27 Collision 27 Loopback 27 Operational 27 Test Loopback 27 Configuration Management Interface 28 MII Management Interface 28 MII Addressing 29 Hardware Control 30 Operating 30 Power Requirements 30 Clock Requirements 30 Reference Clock / External Oscillator 30 MDIO 31 Initialization 31 MDIO Control 31 Hardware Control 31 Power-Down Mode 31 Hardware 32 Software Power-Down 32 Reset 32 Hardware Configuration 32 Link 33 Auto-Negotiation 33 Base Page Exchange 33 Next Page Exchange 34 Controlling Auto-Negotiation 34 Link 34 Parallel 34 Network Media/Protocol Support 35 10/100 Mbps Network 35 Twisted-Pair 35 Fiber 36 Fault Detection and Reporting 36 Product Ordering Information 95 Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 5 Figures Figures 1 Block 13 2 Pin 14 3 25 4 Loopback Paths 28 5 Management Interface Read Frame Structure 29 6 Management Interface Write Frame Structure 29 7 Port Address Scheme 30 8 Auto-Negotiation Operation 35 9 100BASE-X Frame Format 37 10 Protocol Sublayers 38 11 Typical LED Implementation 41 12 Power and Ground Supply Connections 46 13 Typical Twisted-Pair Interface 47 14 Recommended LXT973 Transceiver-to-3.3 V Fiber Transceiver Interface Circuitry 48 15 Recommended LXT973 Transceiver-to-5 V Fiber Transceiver Interface Circuitry........................ 49 16 ON Semiconductor* Triple PECL-to-LVPECL Logic Translator 50 17 Typical MII Interface 50 18 Initialization 51 19 100BASE-TX Frame Format 57 20 100BASE-TX Data Path 57 21 100BASE-TX Reception with no 58 22 100BASE-TX Reception with Invalid Symbol 59 23 100BASE-TX Transmission with no 59 24 100BASE-TX Transmission with 59 25 MII 10BASE-T DTE Mode 63 26 100BASE-T DTE Mode 63 27 Link Down Clock Transition 64 28 PHY Identifier Bit Mapping 68 29 100BASE-TX Transmit Timing - 4B 81 30 100BASE-TX Receive Timing - 4B 82 31 100BASE-FX Transmit Timing 83 32 100BASE-FX Receive Timing 84 33 10BASE-T Transmit Timing Parallel Mode 85 34 10BASE-T Receive Timing Parallel Mode 86 35 10BASE-T SQE Heartbeat Timing 87 Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 6 Figures 36 10BASE-T Jab and Unjab 87 37 Fast Link Pulse Timing 88 38 FLP Burst 88 39 MDIO Input Timing 89 40 MDIO Output 89 41 Power-Up 90 42 RESET Pulse Width and Recovery Timing 90 43 Mechanical Specifications 92 44 Example of Top Marking Information Labeled as Cortina Systems, 93 45 Sample PQFP Package marked as Intel* LXT973QC Transceiver 93 46 Sample Pb-Free RoHS-Compliant PQFP Package marked as Intel* Intel* EGLX973QC Transceiver 94 47 Ordering Information Sample 96 Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 7 Tables Tables 1 PQFP Pin List 15 2 Port 0 Signal Descriptions 18 3 Port 1 Signal Descriptions 19 4 Network Interface Signal 20 5 Global Control & Configuration Signal Descriptions 21 6 Power Supply Signal 22 7 Per Port LED and Configuration Signal Descriptions 22 8 Carrier Sense, Loopback, and Collision Conditions 28 9 Configuration Settings Hardware Control 33 10 LED Configurations 41 11 Magnetics 45 12 Mode Control Settings 52 13 Configuration Settings Hardware Control 53 14 Common Register Set 65 15 Register Bit Descriptions 65 16 Control Register Address 0 66 17 Status Register Address 1 67 18 PHY Identification Register 1 Address 2 68 19 PHY Identification Register 2 Address 3 68 20 Auto-Negotiation Advertisement Register Address 69 21 Auto-Negotiation Link Partner Base Page Ability Register Address 5 70 22 Auto-Negotiation Expansion Register Address 6 71 23 Auto-Negotiation Next Page Transmit Register Address 7 71 24 Auto-Negotiation Link Partner Next Page Ability Register Address 8 72 25 Port Configuration Register Address 72 26 Special Function Register Address 27 73 27 Magnetics 75 28 Absolute Maximum 76 29 Operating 76 30 Digital Input/Output Characteristics2 31 Digital Input/Output Characteristics - SD 77 32 Digital Input/Output Characteristics - MII 78 33 REFCLK 78 34 LED Pin 78 35 100BASE-TX Transceiver 79 Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 8 Tables 36 10BASE-T Transceiver Characteristics 79 37 100BASE-FX Transceiver 79 38 10BASE-T Link Integrity Timing 80 39 Twisted-Pair 80 40 MII - 100BASE-TX Transmit Timing Parameters - 4B Mode 81 41 MII - 100BASE-TX Receive Timing Parameters - 4B Mode 82 42 100BASE-FX Transmit Timing 83 43 100BASE-FX Receive Timing 84 44 MII - 10BASE-T Transmit Timing Parameters Parallel 85 45 MII - 10BASE-T Receive Timing Parameters Parallel 86 46 10BASE-T SQE Heartbeat Timing Parameters 87 47 10BASE-T Jab and Unjab Timing Parameters 87 48 Fast Link Pulse Timing 88 49 MDIO Timing 89 50 Power-Up Timing Parameters 90 51 RESET Pulse Width and Recovery Timing 91 52 Product Ordering Information 95 Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 9 • Changed the following signal names throughout the datasheet: Changed From DPAP/N_0 DPBP/N_0 DPBP/N_1 DPAP/N_1 Changed To DIFAP/N_0 DIFBP/N_0 DIFAP/N_1 DIFBP/N_1 • The pair type on pins 67 and 68 were changed to “A” in Table • The pair type on pins 71 and 72 were changed to “B” in Table Updated the product top marking diagrams First release of this document from Cortina Systems, Inc. Modified Figure 2, Pin Assignments, on page Added Section Top Label Marking, on page Modified Table 52, Product Ordering Information, on page Modified Figure 47, Ordering Information Sample, on page First paragraph Modified first sentence Modified third sentence - Changed "pseudo-ECL" to "Low Voltage PECL Removed bullet under Product Features Integrated termination resistors. Modified descriptions for pins 35, 36, 93, and 94 in Table 2 “LXT973 Port 0 Signal Descriptions”. Changed the last word for SD0 and SD1 under Description from "Low" to “GND” in Table 4 “LXT973 Network Interface Signal Descriptions”. Modified descriptions for pins 7 and 8 in Table 7 “LXT973 Per Port LED and Configuration Signal Descriptions”. Changed PECL to LVPECL in second to last sentence in the first paragraph under Section “Introduction”. Replaced text under Section “Fiber Interface”. Modified text in second paragraph under Section “Power-Down Mode”. Modified bullets under Section “Hardware Power-Down”. Changed Register 11 to Register bit under Section “Software Power-Down”. Changed PECL to LVPECL in third paragraph, first sentence under Section “100BASE-X Network Operations”. Modified Figure 10 “Protocol Sublayers” changed "PECL Interface" to "LVPECL Interface". Replaced text under Section “Fiber PMD Sublayer”. Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 10 Modified first sentence under Section “MII Terminations”. Replaced text under Section “The Fiber Interface”. Modified text under Section “Magnetics Information”. Replaced Figure 14 “Recommended LXT973-to-3.3 VFiber Transceiver Interface Circuitry”. Added Figure 15 “Recommended LXT973-to-5 VFiber Transceiver Interface Circuitry”. Added Figure 16 “ON Semiconductor* Triple PECL-to-LVPECL Logic Translator”. Changed PECL to LVPECL in first paragraph, second sentence under Section “Fiber Interface”. Modified table note 2 in Table 29 “Port Configuration Register Address 16 ” changed ”hardware pins” to “FIBER_TPn”. Modified table note 2 in Table 41 “Digital Input/Output Characteristics2” changed “applies to all pins except MII...” to “applies to all pins except SD, MII...”. Added Table 42 “Digital Input/Output Characteristics - SD Pins”. In Table 46 “100BASE-TX Transceiver Characteristics” Changed "Peak differential output voltage single ended " to "Peak-to-peak differential output voltage". Changed "VOP" to "Vdiffp-p", and removed footnote #2 and all references . Modified Table 63 “Product Ordering Information”. Figure 1 “LXT973 Block Diagram” Added note to diagram. Under Section “PMA Sublayer” Removed Table 10 4B/5B Coding. Section “Monitoring Auto-Negotiation” Removed paragraphs 3 and 4, and Figure Under Section “Displaying Symbol Errors” Removed Table 16 4B/5B Coding. Section “Register Definitions” Removed “multiple 11-bit registers, with” from first sentence. Table 20 “PHY Identification Register 2 Address 3 ” Changed default for Register bits from “001110” to Table 29 “Absolute Maximum Ratings” Modified Power Supply added VCCA, VCC, VCCPECL, VCCIO information. Added three table notes. Table 31 “Digital Input/Output Characteristics2”Modified table note Table 32 “Digital Input/Output Characteristics - MII Pins” Removed “Driver Output Impedance.” Table 34 “LED Pin Characteristics” Added MAX value to Output High Current. Table 35 “100BASE-TX Transceiver Characteristics” Added Typ values. Table 36 “10BASE-T Transceiver Characteristics” Added/replaced Typ values. Removed “Receiver Input Impedance.” Table 37 “100BASE-FX Transceiver Characteristics” Added Typ values Table 38 “10BASE-T Link Integrity Timing Characteristics” Added Typ value for Link Pulse Width Added Table 39 “Twisted-Pair Pins”. Modified Table 40 on page 77 through Table 49 on page Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 11 Added Figure 39 “Power-Up Timing” and Table 50 “Power-Up Timing Parameters”. Added Figure 40 “RESET Pulse Width and Recovery Timing” and Table 51 “RESET Pulse Width and Recovery Timing Parameters” Section A, “Product Ordering Information” Added product ordering information table and diagram. Initial Release Preliminary datasheet Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 12 Figure 1 Block diagram Note See Table 4, Network Interface Signal Descriptions, on page 20 and Table 5, Global Control & Configuration Signal Descriptions, on page 21 for complete network interface signal configurations Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 13 Pin Assignments and Signal Descriptions Pin Assignments and Signal Descriptions Figure 2 Pin Assignments Package Topside Markings Marking Definition LXT973 Transceiver is the unique identifier for this product family. Identifies the particular silicon “stepping” Refer to Specification Update for additional stepping information. Identifies the batch. Identifies the Finish Process Order. Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 14 Pin Assignments and Signal Descriptions Table 1 PQFP Pin List Sheet 1 of 3 Signal Names Type1 Reference for Full Description TXD1_2 Table 3 on page 19 TXD1_3 COL1 I O, TS Table 3 on page 19 Table 3 on page 19 CRS1 AUTO_NEG1 AUTO_NEG0 SD_2P5V/SPEED1 SD_2P5V/SPEED0 DUPLEX1 10 DUPLEX0 11 LED_CGF0 12 LED_CGF1 13 RESET Product Ordering Information Table 52 Product Ordering Information Table 52 lists the LXT973 Transceiver product ordering information. Figure 47 provides the ordering information matrix. Product Ordering Information Number SLXT973QC.A3V EGLXT973QC.A3V SLXT973QE.A3V EGLXT973QE.A3V Package Type PQFP Pin Count No Yes No Yes Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 95 Figure 47 Ordering Information Sample 973 QP C Product Ordering Information Temperature Range A = Ambient 0 550 C = Commercial 0 700 C E = Extended -40 850 C Internal Package Designator L = LQFP P = PLCC N = DIP Q = PQFP H = QFP T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA BGA with heat slug Product Code = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device MAC/Framer IXP = Network processor Intel Package Designator Pb-Free WB WJ BJ JA WD QU EG WG UB UC EP EE RU PC EL PR LU EW WF JP SC Package HQFP LQFP TQFP PQFP QFN PDIP SSOP PLCC MMAP PBGA CBGA FCBGA TBGA Leaded HB DJ FA HD KU S HG LB PD PA N HZ RC FL FW GD GW HF HL TL B5436-01 Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver Page 96 For additional product and ordering information: ~ End of Document ~

PDF Datasheet Preview

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Datasheet

The Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver LXT973 Transceiver is an IEEE compliant, dual-port, Fast Ethernet PHY transceiver that directly supports both 100BASE-TX and 10BASE-T applications. Each port provides a Media Independent Interface MII for easy attachment to 10 Mbps and 100 Mbps Media Access Controllers MACs . The LXT973 Transceiver also provides a Low-Voltage Positive Emitter Coupled Logic LVPECL interface per port for use with 100BASE-FX fiber networks. The LXT973 Transceiver incorporates the auto MDI/MDIX feature, allowing it to automatically switch twisted-pair inputs and outputs. The LXT973 Transceiver is an ideal building block for systems that require two Ethernet ports, such as Internet Protocol IP Telephones, Twisted-Pair TX -to-Fiber FX converter modules, and for telecom applications, such as Telecom Central Office TCO and Customer Premise Equipment CPE devices. The LXT973 Transceiver supports full-duplex operation at both 10 Mbps and 100 Mbps. Its operating modes can be set using auto-negotiation, parallel detection, or manual control.

Enterprise switches IP telephony switches

Storage Area Networks Multi-port Network Interface Cards NICs

Product Features

Dual-port Fast Ethernet PHY
20 MHz Register Access

Voperation I/O compatibility Low power consumption 250 mW per port
typical

Configurable via MDIO port or external control pins

Integrated termination resistors 100-pin Plastic Quad Flat Package PQFP

Full dual-port MII interface with extended registers

Auto MDI/MDIX switch over capability
• Commercial 0 C to 70 C ambient

SLXT973QC Transceiver EGLXT973QC Transceiver RoHS Compliant

Signal Quality Error SQE enable/disable 100BASE-FX fiber-optic capability on both ports Supports both auto-negotiation systems and
legacy systems without auto-negotiation capability
• -40 C to +85 C ambient Extended

SLXT973QE Transceiver EGLXT973QE Transceiver RoHS Compliant

Support for Next Page

Legal Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA PRODUCTS.

NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

CORTINA , and the Cortina Earth Logo are trademarks or registered trademarks of Cortina Systems, Inc. or its subsidiaries in the US and other countries. Any other product and company names are the trademarks of their respective owners.

Copyright Cortina Systems, Inc. All rights reserved.

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Contents

Contents

Pin Assignments and Signal Descriptions 14

Signal Descriptions 18

Functional 24

Introduction 24 Comprehensive Functionality 24

Interface Descriptions 24 10/100 Mbps Network 24 Twisted-Pair Interface 25 MDI Crossover 26 Fiber 26

MII Operation 26 MII Clocks 26 Transmit 26 Receive Data Valid 26 Carrier 27 Error Signals 27 Collision 27 Loopback 27 Operational 27 Test Loopback 27 Configuration Management Interface 28 MII Management Interface 28 MII Addressing 29 Hardware Control 30

Operating 30 Power Requirements 30 Clock Requirements 30 Reference Clock / External Oscillator 30 MDIO 31

Initialization 31 MDIO Control 31 Hardware Control 31 Power-Down Mode 31 Hardware 32 Software Power-Down 32 Reset 32 Hardware Configuration 32

Link 33 Auto-Negotiation 33 Base Page Exchange 33 Next Page Exchange 34 Controlling Auto-Negotiation 34 Link 34 Parallel 34

Network Media/Protocol Support 35 10/100 Mbps Network 35 Twisted-Pair 35 Fiber 36 Fault Detection and Reporting 36
Product Ordering Information 95

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 5

Figures

Figures
1 Block 13 2 Pin 14 3 25 4 Loopback Paths 28 5 Management Interface Read Frame Structure 29 6 Management Interface Write Frame Structure 29 7 Port Address Scheme 30 8 Auto-Negotiation Operation 35 9 100BASE-X Frame Format 37 10 Protocol Sublayers 38 11 Typical LED Implementation 41 12 Power and Ground Supply Connections 46 13 Typical Twisted-Pair Interface 47 14 Recommended LXT973 Transceiver-to-3.3 V Fiber Transceiver Interface Circuitry 48 15 Recommended LXT973 Transceiver-to-5 V Fiber Transceiver Interface Circuitry........................ 49 16 ON Semiconductor* Triple PECL-to-LVPECL Logic Translator 50 17 Typical MII Interface 50 18 Initialization 51 19 100BASE-TX Frame Format 57 20 100BASE-TX Data Path 57 21 100BASE-TX Reception with no 58 22 100BASE-TX Reception with Invalid Symbol 59 23 100BASE-TX Transmission with no 59 24 100BASE-TX Transmission with 59 25 MII 10BASE-T DTE Mode 63 26 100BASE-T DTE Mode 63 27 Link Down Clock Transition 64 28 PHY Identifier Bit Mapping 68 29 100BASE-TX Transmit Timing - 4B 81 30 100BASE-TX Receive Timing - 4B 82 31 100BASE-FX Transmit Timing 83 32 100BASE-FX Receive Timing 84 33 10BASE-T Transmit Timing Parallel Mode 85 34 10BASE-T Receive Timing Parallel Mode 86 35 10BASE-T SQE Heartbeat Timing 87

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 6

Figures
36 10BASE-T Jab and Unjab 87 37 Fast Link Pulse Timing 88 38 FLP Burst 88 39 MDIO Input Timing 89 40 MDIO Output 89 41 Power-Up 90 42 RESET Pulse Width and Recovery Timing 90 43 Mechanical Specifications 92 44 Example of Top Marking Information Labeled as Cortina Systems, 93 45 Sample PQFP Package marked as Intel* LXT973QC Transceiver 93 46 Sample Pb-Free RoHS-Compliant PQFP Package marked as Intel*
Intel* EGLX973QC Transceiver 94 47 Ordering Information Sample 96

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 7

Tables

Tables
1 PQFP Pin List 15 2 Port 0 Signal Descriptions 18 3 Port 1 Signal Descriptions 19 4 Network Interface Signal 20 5 Global Control & Configuration Signal Descriptions 21 6 Power Supply Signal 22 7 Per Port LED and Configuration Signal Descriptions 22 8 Carrier Sense, Loopback, and Collision Conditions 28 9 Configuration Settings Hardware Control 33 10 LED Configurations 41 11 Magnetics 45 12 Mode Control Settings 52 13 Configuration Settings Hardware Control 53 14 Common Register Set 65 15 Register Bit Descriptions 65 16 Control Register Address 0 66 17 Status Register Address 1 67 18 PHY Identification Register 1 Address 2 68 19 PHY Identification Register 2 Address 3 68 20 Auto-Negotiation Advertisement Register Address 69 21 Auto-Negotiation Link Partner Base Page Ability Register Address 5 70 22 Auto-Negotiation Expansion Register Address 6 71 23 Auto-Negotiation Next Page Transmit Register Address 7 71 24 Auto-Negotiation Link Partner Next Page Ability Register Address 8 72 25 Port Configuration Register Address 72 26 Special Function Register Address 27 73 27 Magnetics 75 28 Absolute Maximum 76 29 Operating 76 30 Digital Input/Output Characteristics2 31 Digital Input/Output Characteristics - SD 77 32 Digital Input/Output Characteristics - MII 78 33 REFCLK 78 34 LED Pin 78 35 100BASE-TX Transceiver 79

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 8

Tables
36 10BASE-T Transceiver Characteristics 79 37 100BASE-FX Transceiver 79 38 10BASE-T Link Integrity Timing 80 39 Twisted-Pair 80 40 MII - 100BASE-TX Transmit Timing Parameters - 4B Mode 81 41 MII - 100BASE-TX Receive Timing Parameters - 4B Mode 82 42 100BASE-FX Transmit Timing 83 43 100BASE-FX Receive Timing 84 44 MII - 10BASE-T Transmit Timing Parameters Parallel 85 45 MII - 10BASE-T Receive Timing Parameters Parallel 86 46 10BASE-T SQE Heartbeat Timing Parameters 87 47 10BASE-T Jab and Unjab Timing Parameters 87 48 Fast Link Pulse Timing 88 49 MDIO Timing 89 50 Power-Up Timing Parameters 90 51 RESET Pulse Width and Recovery Timing 91 52 Product Ordering Information 95

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 9
• Changed the following signal names throughout the datasheet:

Changed From

DPAP/N_0 DPBP/N_0 DPBP/N_1 DPAP/N_1

Changed To

DIFAP/N_0 DIFBP/N_0 DIFAP/N_1 DIFBP/N_1
• The pair type on pins 67 and 68 were changed to “A” in Table
• The pair type on pins 71 and 72 were changed to “B” in Table

Updated the product top marking diagrams

First release of this document from Cortina Systems, Inc.
Modified Figure 2, Pin Assignments, on page Added Section Top Label Marking, on page Modified Table 52, Product Ordering Information, on page Modified Figure 47, Ordering Information Sample, on page

First paragraph Modified first sentence Modified third sentence - Changed "pseudo-ECL" to "Low Voltage PECL Removed bullet under Product Features Integrated termination resistors.

Modified descriptions for pins 35, 36, 93, and 94 in Table 2 “LXT973 Port 0 Signal Descriptions”.

Changed the last word for SD0 and SD1 under Description from "Low" to “GND” in Table 4 “LXT973 Network Interface Signal Descriptions”.

Modified descriptions for pins 7 and 8 in Table 7 “LXT973 Per Port LED and Configuration Signal Descriptions”.

Changed PECL to LVPECL in second to last sentence in the first paragraph under Section “Introduction”.

Replaced text under Section “Fiber Interface”.

Modified text in second paragraph under Section “Power-Down Mode”.

Modified bullets under Section “Hardware Power-Down”.

Changed Register 11 to Register bit under Section “Software Power-Down”.

Changed PECL to LVPECL in third paragraph, first sentence under Section “100BASE-X Network Operations”.

Modified Figure 10 “Protocol Sublayers” changed "PECL Interface" to "LVPECL Interface".

Replaced text under Section “Fiber PMD Sublayer”.

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 10

Modified first sentence under Section “MII Terminations”.

Replaced text under Section “The Fiber Interface”.

Modified text under Section “Magnetics Information”.

Replaced Figure 14 “Recommended LXT973-to-3.3 VFiber Transceiver Interface Circuitry”.

Added Figure 15 “Recommended LXT973-to-5 VFiber Transceiver Interface Circuitry”.

Added Figure 16 “ON Semiconductor* Triple PECL-to-LVPECL Logic Translator”.

Changed PECL to LVPECL in first paragraph, second sentence under Section “Fiber Interface”.

Modified table note 2 in Table 29 “Port Configuration Register Address 16 ” changed ”hardware pins” to “FIBER_TPn”.

Modified table note 2 in Table 41 “Digital Input/Output Characteristics2” changed “applies to all pins except MII...” to “applies to all pins except SD, MII...”.

Added Table 42 “Digital Input/Output Characteristics - SD Pins”.
In Table 46 “100BASE-TX Transceiver Characteristics” Changed "Peak differential output voltage single ended " to "Peak-to-peak differential output voltage". Changed "VOP" to "Vdiffp-p", and removed footnote #2 and all references . Modified Table 63 “Product Ordering Information”.

Figure 1 “LXT973 Block Diagram” Added note to diagram.

Under Section “PMA Sublayer” Removed Table 10 4B/5B Coding.

Section “Monitoring Auto-Negotiation” Removed paragraphs 3 and 4, and Figure

Under Section “Displaying Symbol Errors” Removed Table 16 4B/5B Coding.

Section “Register Definitions” Removed “multiple 11-bit registers, with” from first sentence.

Table 20 “PHY Identification Register 2 Address 3 ” Changed default for Register bits from “001110” to

Table 29 “Absolute Maximum Ratings” Modified Power Supply added VCCA, VCC, VCCPECL, VCCIO information. Added three table notes.

Table 31 “Digital Input/Output Characteristics2”Modified table note

Table 32 “Digital Input/Output Characteristics - MII Pins” Removed “Driver Output Impedance.”

Table 34 “LED Pin Characteristics” Added MAX value to Output High Current.

Table 35 “100BASE-TX Transceiver Characteristics” Added Typ values.

Table 36 “10BASE-T Transceiver Characteristics” Added/replaced Typ values. Removed “Receiver Input Impedance.”

Table 37 “100BASE-FX Transceiver Characteristics” Added Typ values

Table 38 “10BASE-T Link Integrity Timing Characteristics” Added Typ value for Link Pulse Width

Added Table 39 “Twisted-Pair Pins”.

Modified Table 40 on page 77 through Table 49 on page

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 11

Added Figure 39 “Power-Up Timing” and Table 50 “Power-Up Timing Parameters”.

Added Figure 40 “RESET Pulse Width and Recovery Timing” and Table 51 “RESET Pulse Width and Recovery Timing Parameters”
Section A, “Product Ordering Information” Added product ordering information table and diagram.

Initial Release Preliminary datasheet

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 12

Figure 1

Block diagram

Note See Table 4, Network Interface Signal Descriptions, on page 20 and Table 5, Global Control & Configuration Signal Descriptions, on page 21 for complete network interface signal configurations

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 13

Pin Assignments and Signal Descriptions

Pin Assignments and Signal Descriptions

Figure 2

Pin Assignments

Package Topside Markings

Marking

Definition

LXT973 Transceiver is the unique identifier for this product family. Identifies the particular silicon “stepping” Refer to Specification Update for additional stepping information. Identifies the batch. Identifies the Finish Process Order.

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 14

Pin Assignments and Signal Descriptions

Table 1

PQFP Pin List Sheet 1 of 3

Signal Names

Type1

Reference for Full Description

TXD1_2

Table 3 on page 19

TXD1_3

COL1

I O, TS

Table 3 on page 19 Table 3 on page 19

CRS1

AUTO_NEG1

AUTO_NEG0

SD_2P5V/SPEED1

SD_2P5V/SPEED0

DUPLEX1
10 DUPLEX0
11 LED_CGF0
12 LED_CGF1
13 RESET
Product Ordering Information

Table 52
Product Ordering Information
Table 52 lists the LXT973 Transceiver product ordering information. Figure 47 provides the ordering information matrix.
Product Ordering Information

Number

SLXT973QC.A3V EGLXT973QC.A3V SLXT973QE.A3V EGLXT973QE.A3V

Package Type

PQFP

Pin Count

No Yes No Yes

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 95
Figure 47 Ordering Information Sample
973 QP C
Product Ordering Information

Temperature Range A = Ambient 0 550 C = Commercial 0 700 C E = Extended -40 850 C

Internal Package Designator L = LQFP P = PLCC N = DIP Q = PQFP H = QFP T = TQFP B = BGA C = CBGA E = TBGA K = HSBGA BGA with heat slug

Product Code = 3-5 Digit alphanumeric

IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device MAC/Framer IXP = Network processor

Intel Package Designator

Pb-Free

WB WJ BJ JA WD QU EG WG UB UC EP EE RU PC EL PR LU EW WF JP SC

Package

HQFP LQFP TQFP PQFP QFN PDIP SSOP PLCC MMAP PBGA CBGA FCBGA TBGA

Leaded

HB DJ FA HD KU S HG LB PD PA N HZ RC FL FW GD GW HF HL TL

B5436-01

Cortina LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver

Page 96
For additional product and ordering information:
~ End of Document ~

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Datasheet ID: EGLXT973QEA3V-873108 506896