PEF 24901 H V2.2

PEF 24901 H V2.2 Datasheet


Quad ISDN 4B3T Echocanceller Digital Front End PEF 24901, Version

Part Datasheet
PEF 24901 H V2.2 PEF 24901 H V2.2 PEF 24901 H V2.2 (pdf)
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Data Sheet, DS1, Sep. 2002

DFE-T V2.2

Quad ISDN 4B3T Echocanceller Digital Front End PEF 24901, Version

Wired Communications

Never stop thinking.

Edition 2002-09-30

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

Infineon Technologies AG

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer.

Information

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Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

DFE-T PEF 24901

Data Sheet
2002-09-30

Previous Version:

Preliminary Data Sheet, DS1,
update related documents
conforms to ITU-T G.961 not ITU-T I.430 removed transparent channel

Removed Sophisticated power management for restricted power mode Removed Monitor Time-Out MTO procedure ’LTD’ supported Coefficients are no more retrievable by MON-8 commands

Figure 2, Figure 6, Table 1
logic symbol, pin conf., pin definitions removed TP1, MTO 49, 53 no function, may be clamped to GND or VDD, respectively, for compatibility to former versions
added DELIC-PB, restriction on DELIC-PB, added Vbat, removed solution with ELIC/IDEC is discontinued

Page 19
added note on CLOCK and FSC from same source

Figure 4
added connection between pin CLOCK and FSC

Table 1, Table 2
changed pins CLS indicate 1 ms clock of the received frame.

Table 1
added footnote to PU/PD to TCK in case that JTAG is reset e.g. pull-down 47

Table 1
removed from all PD/PU-pins internal pullup 160 added footnote to PU/PD e.g. 10 to 20

Table 1
removed from PUP as soon as 1.FSC was received after reset
updated pinning changes

Table 3
added new table ’pin controlled test modes’
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Datasheet ID: PEF24901HV2.2 638453