PEF 2054 N V2.1

PEF 2054 N V2.1 Datasheet

Extended PCM Interface Controller PEB 2055 / PEF 2055 Versions A3 PEB 2054 / PEF 2054 Versions

Part	Datasheet
PEF 2054 N V2.1	PEF 2054 N V2.1 (pdf)

Related Parts	Information
PEF 2055 N V2.1	PEF 2055 N V2.1

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ICs for Communications Extended PCM Interface Controller PEB 2055 / PEF 2055 Versions A3 PEB 2054 / PEF 2054 Versions User’s Manual Previous Release: Page in Previous Release Page in User’s Manual Edition This edition was realized using the software system Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München Siemens AG All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list . Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended a to be implanted in the human body, or b to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PEB 2055 PEF 2055 Table of Contents Overview Pin Configuration Pin Definitions and Functions Logic Symbols Functional Block Diagram Using the EPIC-S System Integration and Application Digital Line Card Switching, Layer-1 Control Decentralized D-Channel Handling Central D-Channel Processing Mixed D-Channel Processing, Signaling Decentralized, Packet Data Centralized Analog Line Card Packet Handlers Functional Description Bus Interface PCM Interface Configurable Interface Memory Structure and Switching Pre-processed Channels, Layer-1 Support Special Functions Operational Description Microprocessor Interface Operation Clocking Reset Operation Ordering Code Q67100-H6035 Q67100-H6216 Q67100-H6420 Q67100-H6534-B701 Package P-LCC-44-1 P-LCC-44-1 P-LCC-44-1 P-LCC-44-1 PEB 2055 PEF 2055 Overview Handling of Layer-1 Functions • Change detection for C/I-channel IOM-configuration or feature control SLD-configuration • Double last-look logic for C/I-channel IOM-2 analog configuration • Additional last-look logic for feature control SLD-configuration • Buffered monitor IOM-configuration or signaling channel SLD-configuration Bus Interface • Siemens/Intel or Motorola type µP-interface • 8-bit demultiplexed bus interface • FIFO-access interrupt or DMA controlled Pin Configuration top view DS/RD VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A2 28 27 26 25 24 23 22 21 20 19 18 R/W,WR 29 CS 30 ALE 31 INT 32 DCL 33 FSC 34 DU3/SIP7 35 DU2/SIP6 36 DU1/SIP5 37 DU0/SIP4 38 A3 39 PEB 2055 EPIC R 17 PDC 16 PFS 15 TxD3 14 TSC3 13 TxD2 12 TSC2 11 TxD1 10 TSC1 9 TxD0 8 TSC0 7 A1 40 41 42 43 44 1 2 3 4 5 6 DD0/SIP0 DD1/SIP1 DD2/SIP2 DD3/SIP3 RES VDD A0 RxD3 RxD2 RxD1 RxD0 ITP09463 Figure 1 Pin Configuration Semiconductor Group PEB 2055 PEF 2055 Overview DS/RD VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A2 28 27 26 25 24 23 22 21 20 19 18 R/W,WR 29 CS 30 ALE 31 INT 32 DCL 33 FSC 34 N.C. 35 N.C. 36 DU1 37 DU0 38 A3 39 PEB 2054 EPIC R-S 17 PDC 16 PFS 15 TxD3 14 TSC3 13 TxD2 12 TSC2 11 TxD1 10 TSC1 9 TxD0 8 TSC0 7 A1 40 41 42 43 44 1 2 3 4 5 6 DD0 DD1 N.C. N.C. RES VDD A0 RxD3 RxD2 RxD1 RxD0 ITP09530 Figure 2 Pin Configuration Semiconductor Group PEB 2055 PEF 2055 Overview Pin Definitions and Functions Pin No. Symbol Input I Function EPIC-S EPIC Output O 30 CS Chip Select active low. A “low” on this line selects the EPIC for read/write operations. Ordering Code Q67100-H8647 SAC 3 SAC 2 SAC 1 AMC 3 80C188 CPU System AMC 2 Dual Port RAM AMC 1 PC Interface ITB05758 Figure 105 SIPB_5000 Mainboard The SIPB 5000 Mainboard is the general backbone of the SIPB 5XXX user board system. It is designed as a standard PC interface card, and it contains basically a 80C188 CPU system with 7 interfaces. The interface to the PC is realized both as a Dual Port Ram and as an additional DMA interface. Up to three daughter modules see dotted blocks can be added to the Mainboard. They typically carry the components under evaluation. The interfaces which are accessible from the back side of the PC have a connection to the daughter modules as well. This is to allow access to the components under evaluation while the complete board system is hidden inside the PC. Semiconductor Group SIPB 5121 Line Card PEB 2055 PEF 2055 Description IOM-2 Line Card Module Part Number SIPB 5121 Ordering Code Q67100-H8656 SLD / IOM R /PCM EPIC R PEB 2055 SAC AMC IDEC R PEB 2075 IDEC R PEB 2075 HSCX SAB 82525 ITB05759 Figure 106 SIPB 5121 Line Card The Line Card Module SIBP 5121 is designed to be used with the ISDN User Board SIPB It serves as an evaluation tool for various line card architectures using the Enhanced PCM Interface Controller EPIC PEB Some possible applications are e.g.: Centralized / decentralized D-channel handling of signaling and packet data Emulation of a PABX with primary rate module SIPB 7200 Emulation of a small PABX using two line cards Emulation of a digital or analog line card using appropriate layer-1 and/or CODEC filter modules Semiconductor Group Configurator PEB 2055 PEF 2055 Figure 107 Configuration Tool Screen Shot The EPIC Configurator is an expert system which helps to initialize the IOM-2 controllers: • PEB 2015 MICO • PEB 2054 EPIC-S • PEB 2055 EPIC-1 • PEB 2055 ELIC only functional units EPIC, SACCO-A + arbiter A menu driven software allows the user to define the system requirements on a functional level. The Configurator then generates a programming sequence in C code for initializing the EPIC, providing all required register values. Semiconductor Group Lists Glossary Audio ringing codec filter Bits per PCM frame Configurable interface Control memory Central office Data clock Extended PCM interface controller ETSI European telecommunication standards institute FIFO First-in first-out memory Frame synchronisation clock HDLC High-level data link control Integrated circuit Identifier ISDN oriented modular

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ICs for Communications

Extended PCM Interface Controller PEB 2055 / PEF 2055 Versions A3 PEB 2054 / PEF 2054 Versions

User’s Manual

Previous Release:

Page in Previous Release

Page in User’s Manual

Edition This edition was realized using the software system Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG

All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list . Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended a to be implanted in the human body, or b to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

PEB 2055 PEF 2055

Table of Contents

Overview

Pin Configuration

Pin Definitions and Functions

Logic Symbols

Functional Block Diagram

Using the EPIC-S

System Integration and Application

Digital Line Card

Switching, Layer-1 Control

Decentralized D-Channel Handling

Central D-Channel Processing

Mixed D-Channel Processing, Signaling Decentralized,

Packet Data Centralized

Analog Line Card

Packet Handlers

Functional Description

Bus Interface

PCM Interface

Configurable Interface

Memory Structure and Switching

Pre-processed Channels, Layer-1 Support

Special Functions

Operational Description

Microprocessor Interface Operation

Clocking

Reset

Operation
Ordering Code Q67100-H6035 Q67100-H6216 Q67100-H6420 Q67100-H6534-B701

Package P-LCC-44-1 P-LCC-44-1 P-LCC-44-1 P-LCC-44-1

PEB 2055 PEF 2055

Overview

Handling of Layer-1 Functions
• Change detection for C/I-channel IOM-configuration or feature control

SLD-configuration
• Double last-look logic for C/I-channel IOM-2 analog configuration
• Additional last-look logic for feature control SLD-configuration
• Buffered monitor IOM-configuration or signaling channel SLD-configuration

Bus Interface
• Siemens/Intel or Motorola type µP-interface
• 8-bit demultiplexed bus interface
• FIFO-access interrupt or DMA controlled

Pin Configuration top view

DS/RD VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A2
28 27 26 25 24 23 22 21 20 19 18

R/W,WR 29 CS 30 ALE 31 INT 32 DCL 33 FSC 34

DU3/SIP7 35 DU2/SIP6 36 DU1/SIP5 37 DU0/SIP4 38

A3 39

PEB 2055 EPIC R
17 PDC 16 PFS 15 TxD3 14 TSC3 13 TxD2 12 TSC2 11 TxD1 10 TSC1 9 TxD0 8 TSC0 7 A1
40 41 42 43 44 1 2 3 4 5 6

DD0/SIP0 DD1/SIP1 DD2/SIP2 DD3/SIP3

RES VDD A0 RxD3 RxD2 RxD1 RxD0

ITP09463

Figure 1 Pin Configuration

Semiconductor Group

PEB 2055 PEF 2055

Overview

DS/RD VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A2
28 27 26 25 24 23 22 21 20 19 18

R/W,WR 29 CS 30 ALE 31 INT 32 DCL 33 FSC 34 N.C. 35 N.C. 36 DU1 37 DU0 38 A3 39

PEB 2054 EPIC R-S
17 PDC 16 PFS 15 TxD3 14 TSC3 13 TxD2 12 TSC2 11 TxD1 10 TSC1 9 TxD0 8 TSC0 7 A1
40 41 42 43 44 1 2 3 4 5 6

DD0 DD1 N.C. N.C. RES VDD A0 RxD3 RxD2 RxD1 RxD0

ITP09530

Figure 2 Pin Configuration

Semiconductor Group

PEB 2055 PEF 2055

Overview

Pin Definitions and Functions

Pin No. Symbol Input I Function

EPIC-S EPIC

Output O
30 CS

Chip Select active low. A “low” on this line selects the EPIC for read/write operations.
Ordering Code Q67100-H8647

SAC 3 SAC 2 SAC 1

AMC 3
80C188 CPU System

AMC 2

Dual Port RAM

AMC 1

PC Interface

ITB05758

Figure 105 SIPB_5000 Mainboard

The SIPB 5000 Mainboard is the general backbone of the SIPB 5XXX user board system. It is designed as a standard PC interface card, and it contains basically a 80C188 CPU system with 7 interfaces. The interface to the PC is realized both as a Dual Port Ram and as an additional DMA interface. Up to three daughter modules see dotted blocks can be added to the Mainboard. They typically carry the components under evaluation. The interfaces which are accessible from the back side of the PC have a connection to the daughter modules as well. This is to allow access to the components under evaluation while the complete board system is hidden inside the PC.

Semiconductor Group

SIPB 5121 Line Card

PEB 2055 PEF 2055

Description IOM-2 Line Card Module

Part Number SIPB 5121
Ordering Code Q67100-H8656

SLD / IOM R /PCM

EPIC R PEB 2055

SAC AMC

IDEC R PEB 2075

IDEC R PEB 2075

HSCX SAB 82525

ITB05759

Figure 106 SIPB 5121 Line Card

The Line Card Module SIBP 5121 is designed to be used with the ISDN User Board SIPB It serves as an evaluation tool for various line card architectures using the Enhanced PCM Interface Controller EPIC PEB

Some possible applications are e.g.:

Centralized / decentralized D-channel handling of signaling and packet data Emulation of a PABX with primary rate module SIPB 7200 Emulation of a small PABX using two line cards Emulation of a digital or analog line card using appropriate layer-1 and/or CODEC
filter modules

Semiconductor Group

Configurator

PEB 2055 PEF 2055

Figure 107 Configuration Tool Screen Shot

The EPIC Configurator is an expert system which helps to initialize the IOM-2 controllers:
• PEB 2015 MICO
• PEB 2054 EPIC-S
• PEB 2055 EPIC-1
• PEB 2055 ELIC only functional units EPIC, SACCO-A + arbiter

A menu driven software allows the user to define the system requirements on a functional level.

The Configurator then generates a programming sequence in C code for initializing the EPIC, providing all required register values.

Semiconductor Group

Lists

Glossary

Audio ringing codec filter

Bits per PCM frame

Configurable interface

Control memory

Central office

Data clock

Extended PCM interface controller

ETSI

European telecommunication standards institute

FIFO

First-in first-out memory

Frame synchronisation clock

HDLC

High-level data link control

Integrated circuit

Identifier

ISDN oriented modular

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Datasheet ID: PEF2054NV2.1 638410