AN985BX-BG-T-V1

AN985BX-BG-T-V1 Datasheet

AN985B/BX

Part	Datasheet
AN985BX-BG-T-V1	AN985BX-BG-T-V1 (pdf)

PDF Datasheet Preview
AN985B/BX CardBus-to-Ethernet LAN Controller Communications Never stop thinking. Edition 2005-11-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Trademarks are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems Incorporated. Template template_A4_3.0.fm / 3 / 2005-01-17 AN985B/BX Table of Contents Table of Contents Table of Contents 4 List of Figures 6 List of Tables 7 General Description 8 System Block Diagram 8 Features 8 Block Diagram 10 Pin Assignment Diagram 11 Pin Type and Buffer Type Abbreviations 12 Pin Description 13 Functional Descriptions 18 Network Packet Buffer Management 18 Descriptor Structure Types 18 The Point of Descriptor Management 19 Transmit Scheme and Transmit Early Interrupt 22 Transmit Flow 22 Transmit Pre-fetch Data Flow 22 Transmit Early interrupt Scheme 23 Receive Scheme and Receive Early Interrupt Scheme 23 Network Operation 24 MAC Operation 24 Transceiver Operation 26 100BASE-TX Transmit Operation 26 100BASE-TX Receiving Operation 27 10BASE-T Transmission Operation 27 10BASE-T Receive Operation 27 Loop-back Operation of Transceiver 27 Full Duplex and Half Duplex Operation of Transceiver 28 Auto-Negotiation Operation 28 Power Down Operation 28 Flow Control in Full Duplex Application 28 LED Display Operation 31 Reset Operation 31 Reset Whole Chip 31 Reset Transceiver Only 31 Wake on LAN Function 31 The Magic Packet Format 31 The Wake on LAN Operation 31 ACPI Power Management Function 31 Power States 32 Registers and Descriptors Description 33 AN985B/BX Configuration Registers 34 AN985B/BX Configuration Registers Descriptions 35 PCI /CARDBUS Control/Status Registers 47 PCI/CARDBUS Control/Status Registers Description 49 Data Sheet AN985B/BX Table of Contents PHY Registers 82 PHY Transceiver Registers Descriptions 83 Descriptors and Buffer Management 93 Receive Descriptor Descriptions 94 Transmit Descriptor Descriptions 98 Electrical Specifications and Timings 101 Absolute Maximum Ratings 101 DC Specifications 101 AC Specifications 102 Timing Specifications 102 Package Outlines 108 Appendix 109 MII Management Access Procedure 109 Debugging Purpose Registers Offset FCH 109 EEPROM DATA TABLE 109 command while being bus master • Supports big or little endian byte ordering EEPROM/Boot ROM I/F • Write-able Flash ROM and EPROM as boot ROM with size up to 128 KB • CARDBUS to access boot ROM by byte, word, or double word • Re-write Flash boot ROM through I/O port by programming register • Serial interface for read/write 93C46/66 EEPROM • Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment • CIS data is recalled from 93C66 to AN985B/BX PC internal SRAM to speed up CIS access in CARDBUS environment MAC/Physical • Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T • Full -duplex operation on both 100 Mbit/s and 10 Mbit/s modes • Auto-negotiation NWAY function of full/half duplex operation for both 10 and 100 Mbit/s • Transmits wave-shaper, receive filters, and adaptive equalizer • MLT-3 transceivers with DC restoration for Base-line wander compensation • MAC and Transceiver TXCVR loop-back modes for diagnostic • Built in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder • External transmitting transformer with turn ratio 1:1 • External receiving transformer with turn ratio 1:1 LED Display • 3 LEDs display scheme provided 100 Mbit/s on or Speed 10 off Link keeps on when link ok or Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding • 4 LEDs displayed scheme provided 100 Mbit/s and Link keep on when link and 100 Mbit/s 10 Mbit/s and Link keep on when link and 10 Mbit/s Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding Miscellaneous • 128-pin QFP package for CARDBUS interface. Data Sheet Block Diagram AN985B/BX Block Diagram Figure 2 Block Diagram of the AN985B/BX Data Sheet Pin Assignment Diagram AN985B/BX Pin Assignment Diagram Figure 3 Pin Assignment top view Data Sheet AN985B/BX Pin Type and Buffer Type Abbreviations Standardized abbreviations: Table 1 Abbreviations for Pin Type Abbreviations Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Output. Analog levels. AI/O Input or Output. Analog levels. Power Ground Must be connected to Low JEDEC Standard Must be connected to High JEDEC Standard Not Usable JEDEC Standard Not Connected JEDEC Standard

PDF Datasheet Preview

AN985B/BX

CardBus-to-Ethernet LAN Controller

Communications

Never stop thinking.

Edition 2005-11-30

Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Trademarks are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems Incorporated.

Template template_A4_3.0.fm / 3 / 2005-01-17

AN985B/BX

Table of Contents

Table of Contents

Table of Contents 4

List of Figures 6

List of Tables 7

General Description 8

System Block Diagram 8

Features 8

Block Diagram 10

Pin Assignment Diagram 11

Pin Type and Buffer Type Abbreviations 12

Pin Description 13

Functional Descriptions 18 Network Packet Buffer Management 18

Descriptor Structure Types 18 The Point of Descriptor Management 19 Transmit Scheme and Transmit Early Interrupt 22 Transmit Flow 22 Transmit Pre-fetch Data Flow 22 Transmit Early interrupt Scheme 23 Receive Scheme and Receive Early Interrupt Scheme 23 Network Operation 24 MAC Operation 24 Transceiver Operation 26
100BASE-TX Transmit Operation 26 100BASE-TX Receiving Operation 27 10BASE-T Transmission Operation 27 10BASE-T Receive Operation 27 Loop-back Operation of Transceiver 27 Full Duplex and Half Duplex Operation of Transceiver 28 Auto-Negotiation Operation 28 Power Down Operation 28 Flow Control in Full Duplex Application 28 LED Display Operation 31 Reset Operation 31 Reset Whole Chip 31 Reset Transceiver Only 31 Wake on LAN Function 31 The Magic Packet Format 31 The Wake on LAN Operation 31 ACPI Power Management Function 31 Power States 32

Registers and Descriptors Description 33 AN985B/BX Configuration Registers 34

AN985B/BX Configuration Registers Descriptions 35 PCI /CARDBUS Control/Status Registers 47

PCI/CARDBUS Control/Status Registers Description 49

Data Sheet

AN985B/BX

Table of Contents

PHY Registers 82 PHY Transceiver Registers Descriptions 83

Descriptors and Buffer Management 93 Receive Descriptor Descriptions 94 Transmit Descriptor Descriptions 98

Electrical Specifications and Timings 101 Absolute Maximum Ratings 101 DC Specifications 101 AC Specifications 102 Timing Specifications 102

Package Outlines 108

Appendix 109 MII Management Access Procedure 109 Debugging Purpose Registers Offset FCH 109 EEPROM DATA TABLE 109
command while being bus master
• Supports big or little endian byte ordering

EEPROM/Boot ROM I/F
• Write-able Flash ROM and EPROM as boot ROM with size up to 128 KB
• CARDBUS to access boot ROM by byte, word, or double word
• Re-write Flash boot ROM through I/O port by programming register
• Serial interface for read/write 93C46/66 EEPROM
• Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and

Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment
• CIS data is recalled from 93C66 to AN985B/BX PC internal SRAM to speed up CIS access in CARDBUS
environment

MAC/Physical
• Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T
• Full -duplex operation on both 100 Mbit/s and 10 Mbit/s modes
• Auto-negotiation NWAY function of full/half duplex operation for both 10 and 100 Mbit/s
• Transmits wave-shaper, receive filters, and adaptive equalizer
• MLT-3 transceivers with DC restoration for Base-line wander compensation
• MAC and Transceiver TXCVR loop-back modes for diagnostic
• Built in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
• External transmitting transformer with turn ratio 1:1
• External receiving transformer with turn ratio 1:1

LED Display
• 3 LEDs display scheme provided 100 Mbit/s on or Speed 10 off Link keeps on when link ok or Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding
• 4 LEDs displayed scheme provided 100 Mbit/s and Link keep on when link and 100 Mbit/s 10 Mbit/s and Link keep on when link and 10 Mbit/s Activity will be blinking with 10 Hz when receiving or transmitting but not collision FD keeps on when in Full duplex mode or Collision will be blinking with 20 Hz when colliding

Miscellaneous
• 128-pin QFP package for CARDBUS interface.

Data Sheet

Block Diagram

AN985B/BX

Block Diagram

Figure 2 Block Diagram of the AN985B/BX

Data Sheet

Pin Assignment Diagram

AN985B/BX

Pin Assignment Diagram

Figure 3 Pin Assignment top view

Data Sheet

AN985B/BX

Pin Type and Buffer Type Abbreviations

Standardized abbreviations:

Table 1 Abbreviations for Pin Type

Abbreviations

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Output. Analog levels.

AI/O

Input or Output. Analog levels.

Power

Ground

Must be connected to Low JEDEC Standard

Must be connected to High JEDEC Standard

Not Usable JEDEC Standard

Not Connected JEDEC Standard

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AN985BX-BG-T-V1 Datasheet file may be downloaded here without warranties.

Datasheet ID: AN985BX-BG-T-V1 637598