PEB20534H10-V21

PEB20534H10-V21 Datasheet

DSCC4 DMA Supported Serial Communication Controller with 4 Channels PEB 20534 Version PEF 20534 Version

Part	Datasheet
PEB20534H10-V21	PEB20534H10-V21 (pdf)

Related Parts	Information
PEB20534H52-V2.1	PEB20534H52-V2.1

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Data Sheet, DS 1, May 2000 DSCC4 DMA Supported Serial Communication Controller with 4 Channels PEB 20534 Version PEF 20534 Version Datacom Never stop thinking. Previous Version: in previous in current Version 429-438 427-435 removed remaining references to command bit GCMDR:IADC corrected timing values #81-#86, #132, #149 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide see our webpage at Edition 2000-05-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list . Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. PEB 20534 PEF 20534 The DMA Supported Serial Communication Controller with 4 Channels DSCC4 is a Multi Protocol Controller for a wide range of data communication and telecommunication applications. This document provides complete reference information on hardware and software related issues as well as on general operation. Organization of this Document This Data Sheet is divided into 15 chapters. It is organized as follows • Chapter 1, Overview Gives a general description of the product, lists the key features, and presents some typical applications. • Chapter 2, Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. • Chapters 3,4,5,6,7 Functional Description These chapters provide detailed descriptions of all DSCC4 internal function blocks. • Chapter 8, Detailed Protocol Descriptions Gives a detailed description of all protocols supported by the serial communication controllers SCCs. • Chapter 9, Reset and Initialization Procedure Gives examples for DSCC4 initialization procedure and operation. • Chapter 10, Detailed Register Description Gives a detailed description of all DSCC4 on chip registers. • Chapter 11, Host Memory Organization Provides an overview of all DSCC4 data structures located in the shared memory • Chapter 12, JTAG Boundary Scan Gives a detailed description of the boundary scan unit. • Chapter 13, Electrical Characteristics Gives a detailed description of all electrical DC and AC characteristics and provides timing diagrams and values for all interfaces. • Chapter 14, Package Outline Data Sheet 2000-05-30 PEB 20534 PEF 20534 Data Sheet 2000-05-30 PEB 20534 PEF 20534 Table of Contents Overview 18 Features 19 Differences between the DSCC4 and the ESCC Family 22 All other memory structures descriptors, interrupt vectors as well as DSCC4 registers are organized DWORD-wise and should be operated by software using 32bit operations only. Therefore no little/big endian ordering mismatches can occur on these structures. However byte ordering in the local memory, as it appears to the PCI bus view, depends on the local bus CPU, memory, PCI bridge realization. Data Sheet 2000-05-30 PEB 20534 PEF 20534 Multi Function Port MFP Multi Function Port MFP The Multi Function Port consists of a set of I/O signal pins and three internal function blocks sharing these signal pins. The function blocks are: • Local Bus Interface LBI • Synchronous Serial Communication Interface SSC • General Purpose I/O Port GPP The MFP is only available in PCI bus operation mode, because in de-multiplexed bus mode, all MFP I/O signals are used for the 32-bit address bus extension. Various configurations allow simultaneous operation of the three function blocks: Peripheral Block LBI 12 LBI Ctrl. 16 LD 15:0 LBI Ctrl. LBI Ctrl. LBI Ctrl. LBI Ctrl. LD 15:0 LD 15:0 LD/LA 15:0 LD/LA 15:0 8 LA 15:8 , GP 15:8 LA 15:8 GP 15:8 GP 15:8 GP 15:8 8 LA 7:0 , GP 7:0 , SSC LA 7:0 Configurations LBI only LA 7:0 SSC LBI + 8 bit GPP LBI + 8 bit GPP + SSC GP 7:0 LBI + 16 bit GPP Figure 23 MFP Configurations Overview The configuration is selected via bit field ’PERCFG’ in register GMODE. The following table shows all supported ’PERCFG’ bit field options also refer to “GMODE Global Mode Register” on Page 241 : Data Sheet 2000-05-30 Table 17 PERCFG 2:0 PEB 20534 PEF 20534 Multi Function Port MFP MFP Configuration via GMODE Register, Bit Field ’PERCFG’: Peripheral Block Configuration The peripheral block basically consists of the functions • Local Bus Interface LBI • General Purpose Port GPP • Synchronous Serial Controller SSC which can be operated in various combinations/configurations. Bit field ’PERCFG’ selects the peripheral configuration and switches the multiplexed signal pins accordingly: PCI Interface Mode DEMUX pin connected to VSS PERCFG Signal Pin Groups 109, 108 ’000’ LA 15..8 LA 7..0 This bit selects whether receive and transmit data buffers are handled with Intel or Motorola like byte ordering: ENDIAN=’0’ The DWORDs of receive and transmit data buffers are evaluated based on a little endian Intel like byte ordering. ENDIAN=’1’ The DWORDs of receive and transmit data buffers are evaluated based on a big endian Motorola like byte ordering. Therefore the byte ordering is automatically swapped by the DMA controller. Note The little/big endian selection byte-swapping effects only DSCC4 operation on receive and transmit data buffer sections. Descriptor reads and writes as well as register access is not effected anyway. DEMUX Burst Enable This bit is only valid if the DSCC4 is running in de-multiplexed bus interface mode, i.e. pin DEMUX connected to VDD3. By default value, the burst functionality is disabled in DEMUX mode and can be enabled via setting this bit. However burst length is limited to 4 DWORDs in DEMUX mode 15 DWORDs in PCI mode : DBE=’0’ Burst functionality is disabled. The DSCC4 will perform all transactions to the host memory using single DWORD read/write bus transfers. DBE=’1’ Burst functionality is enabled. The DSCC4 performs burst transfers for operation on descriptors and data sections like in PCI mode . Burst length is limited to 4 DWORDs maximum. CMODE DMA Control Mode This bit selects between the two global DMA controller mechanisms for handling descriptor chain end conditions: CMODE=’0’ ’HOLD’ bit control mode. The descriptor chain end condition is controlled via the ’HOLD’ bit in each receive/transmit descriptor. CMODE=’1’ Last Receive/Transmit Descriptor Address mode. The descriptor chain end condition is controlled via registers LRDA/LTDA. Data Sheet 2000-05-30 PEB 20534 PEF 20534 Detailed Register Description Table 47 IQLENR0 Interrupt Queue Length Register 0 CPU Accessibility Reset Value Offset Address typical usage: read/write 0000 0000H 000CH written by CPU evaluated by DSCC4 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Interrupt Queues Length Configuration IQSCC0RXLEN IQSCC1RXLEN IQSCC2RXLEN IQSCC3RXLEN Bit 15 14 13 12 11 10 9 8 7 6 5 4 Interrupt Queues Length Configuration IQSCC0TXLEN IQSCC1TXLEN IQSCC2TXLEN 3210 IQSCC3TXLEN Data Sheet 2000-05-30 PEB 20534 PEF 20534 Detailed Register Description IQSCC3 RXLEN IQSCC2 RXLEN IQSCC1 RXLEN IQSCC0 RXLEN

PDF Datasheet Preview

Data Sheet, DS 1, May 2000

DSCC4 DMA Supported Serial Communication Controller with 4 Channels PEB 20534 Version PEF 20534 Version

Datacom

Never stop thinking.

Previous Version:
in previous in current

Version
429-438 427-435
removed remaining references to command bit GCMDR:IADC corrected timing values #81-#86, #132, #149

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide see our webpage at

Edition 2000-05-30

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

Infineon Technologies AG

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list .

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

PEB 20534 PEF 20534

The DMA Supported Serial Communication Controller with 4 Channels DSCC4 is a Multi Protocol Controller for a wide range of data communication and telecommunication applications. This document provides complete reference information on hardware and software related issues as well as on general operation.

Organization of this Document This Data Sheet is divided into 15 chapters. It is organized as follows
• Chapter 1, Overview

Gives a general description of the product, lists the key features, and presents some typical applications.
• Chapter 2, Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals.
• Chapters 3,4,5,6,7 Functional Description These chapters provide detailed descriptions of all DSCC4 internal function blocks.
• Chapter 8, Detailed Protocol Descriptions Gives a detailed description of all protocols supported by the serial communication controllers SCCs.
• Chapter 9, Reset and Initialization Procedure Gives examples for DSCC4 initialization procedure and operation.
• Chapter 10, Detailed Register Description Gives a detailed description of all DSCC4 on chip registers.
• Chapter 11, Host Memory Organization Provides an overview of all DSCC4 data structures located in the shared memory
• Chapter 12, JTAG Boundary Scan Gives a detailed description of the boundary scan unit.
• Chapter 13, Electrical Characteristics Gives a detailed description of all electrical DC and AC characteristics and provides timing diagrams and values for all interfaces.
• Chapter 14, Package Outline

Data Sheet
2000-05-30

PEB 20534 PEF 20534

Data Sheet
2000-05-30

PEB 20534 PEF 20534

Table of Contents

Overview 18 Features 19 Differences between the DSCC4 and the ESCC Family 22
All other memory structures descriptors, interrupt vectors as well as DSCC4 registers are organized DWORD-wise and should be operated by software using 32bit operations only. Therefore no little/big endian ordering mismatches can occur on these structures.
However byte ordering in the local memory, as it appears to the PCI bus view, depends on the local bus CPU, memory, PCI bridge realization.

Data Sheet
2000-05-30

PEB 20534 PEF 20534

Multi Function Port MFP

Multi Function Port MFP

The Multi Function Port consists of a set of I/O signal pins and three internal function blocks sharing these signal pins.

The function blocks are:
• Local Bus Interface LBI
• Synchronous Serial Communication Interface SSC
• General Purpose I/O Port GPP

The MFP is only available in PCI bus operation mode, because in de-multiplexed bus mode, all MFP I/O signals are used for the 32-bit address bus extension.

Various configurations allow simultaneous operation of the three function blocks:

Peripheral Block LBI
12 LBI Ctrl.
16 LD 15:0

LBI Ctrl. LBI Ctrl. LBI Ctrl. LBI Ctrl.

LD 15:0 LD 15:0 LD/LA 15:0 LD/LA 15:0
8 LA 15:8 , GP 15:8

LA 15:8 GP 15:8 GP 15:8 GP 15:8
8 LA 7:0 , GP 7:0 , SSC

LA 7:0

Configurations LBI only

LA 7:0 SSC

LBI + 8 bit GPP LBI + 8 bit GPP + SSC

GP 7:0

LBI + 16 bit GPP

Figure 23 MFP Configurations Overview

The configuration is selected via bit field ’PERCFG’ in register GMODE. The following table shows all supported ’PERCFG’ bit field options also refer to “GMODE Global Mode Register” on Page 241 :

Data Sheet
2000-05-30

Table 17

PERCFG 2:0

PEB 20534 PEF 20534

Multi Function Port MFP

MFP Configuration via GMODE Register, Bit Field ’PERCFG’:

Peripheral Block Configuration

The peripheral block basically consists of the functions
• Local Bus Interface LBI
• General Purpose Port GPP
• Synchronous Serial Controller SSC which can be operated in various combinations/configurations. Bit field ’PERCFG’ selects the peripheral configuration and switches the multiplexed signal pins accordingly:

PCI Interface Mode DEMUX pin connected to VSS PERCFG Signal Pin Groups
109, 108
’000’

LA 15..8

LA 7..0
This bit selects whether receive and transmit data buffers are handled with Intel or Motorola like byte ordering:
ENDIAN=’0’ The DWORDs of receive and transmit data buffers are evaluated based on a little endian Intel like byte ordering.

ENDIAN=’1’
The DWORDs of receive and transmit data buffers are evaluated based on a big endian Motorola like byte ordering. Therefore the byte ordering is automatically swapped by the DMA controller.

Note The little/big endian selection byte-swapping effects only DSCC4 operation on receive and transmit data buffer sections. Descriptor reads and writes as well as register access is not effected anyway.

DEMUX Burst Enable

This bit is only valid if the DSCC4 is running in de-multiplexed bus interface mode, i.e. pin DEMUX connected to VDD3. By default value, the burst functionality is disabled in DEMUX mode and can be enabled via setting this bit. However burst length is limited to 4 DWORDs in DEMUX mode 15 DWORDs in PCI mode :

DBE=’0’

Burst functionality is disabled. The DSCC4 will perform all transactions to the host memory using single DWORD read/write bus transfers.

DBE=’1’

Burst functionality is enabled. The DSCC4 performs burst transfers for operation on descriptors and data sections like in PCI mode . Burst length is limited to 4 DWORDs maximum.

CMODE

DMA Control Mode

This bit selects between the two global DMA controller mechanisms for handling descriptor chain end conditions:

CMODE=’0’ ’HOLD’ bit control mode. The descriptor chain end condition is controlled via the ’HOLD’ bit in each receive/transmit descriptor.

CMODE=’1’ Last Receive/Transmit Descriptor Address mode. The descriptor chain end condition is controlled via registers LRDA/LTDA.

Data Sheet
2000-05-30

PEB 20534 PEF 20534

Detailed Register Description

Table 47 IQLENR0 Interrupt Queue Length Register 0

CPU Accessibility Reset Value Offset Address typical usage:
read/write 0000 0000H 000CH written by CPU evaluated by DSCC4

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Interrupt Queues Length Configuration

IQSCC0RXLEN

IQSCC1RXLEN

IQSCC2RXLEN

IQSCC3RXLEN

Bit 15 14 13 12 11 10 9 8 7 6 5 4

Interrupt Queues Length Configuration

IQSCC0TXLEN

IQSCC1TXLEN

IQSCC2TXLEN
3210

IQSCC3TXLEN

Data Sheet
2000-05-30

PEB 20534 PEF 20534

Detailed Register Description

IQSCC3 RXLEN

IQSCC2 RXLEN

IQSCC1 RXLEN

IQSCC0 RXLEN

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEB20534H10-V21 Datasheet file may be downloaded here without warranties.

Datasheet ID: PEB20534H10-V21 638399