XRT91L82IB

XRT91L82IB Datasheet

XRT91L82

Part	Datasheet
XRT91L82IB	XRT91L82IB (pdf)

Related Parts	Information
XRT91L82IB-F	XRT91L82IB-F

PDF Datasheet Preview
XRT91L82 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER APRIL 2005 The XRT91L82 is a fully integrated SONET/SDH transceiver for OC-48/STM16 applications supporting the use of Forward Error Correction FEC capability. The transceiver includes an on-chip Clock Multiplier Unit CMU , which uses a high frequency PhaseLocked Loop PLL to generate the high-speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery CDR functions by synchronizing its on-chip Voltage Controlled Oscillator VCO to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL system interfaces in both receive and transmit directions. The transmit section includes a 16x9 Elastic Buffer FIFO to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the FIFO_AUTORST register bit can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU and LOCKDET_CDR output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. • SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches, Routers and Switch/Routers • DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment FIGURE BLOCK DIAGRAM OF XRT91L82 OVERFLOW FIFO_RST TXDI[15:0]P/N 16 TXPCLKIP/N TXPCLKOP/N TXCLKO16P/N TXCLKO16SEL STS-48 TRANSCEIVER 16x9 FIFO RLOOPP Div by 16 PISO Parallel Input Serial Output Re-Timer CMU DLOOP RLOOPS RXDO[15:0]P/N RXPCLKOP/N DISRD DISRDCLK TDO TDI TCK TMS TRST SIPO Serial Input Parallel Output 16 Div by 16 JTAG Serial Microprocessor Hardware Control TXOP/N TXSCLKOP/N RXIP/N PFD & Charge Pump INT RESET CS SCLK SDI SDO HOST/HW PIO_CFG [1:0] RLOOPS_PRBSCLR DLOOP LPTIME_NOJA TXSWING TXSCLKOOFF CDRLCKREF SE_REF SEREF_DIS PRBS_EN PRBS_ERR SDEXT POLARITY XRES1P XRES1N LOCKDET_CMU LOCKDET_CDR REF1CLKP/N REF2CLKP/N REFREQSEL1 REFREQSEL0 INTERM/VCXO_IN RXCAP1P RXCAP1N/CPOUT Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510 668-7000 • FAX 510 668-7017 • XRT91L82 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER • / Gbps Transceiver • Targeted for SONET OC-48/SDH STM-16 Applications • Selectable full duplex operation between standard rate of Gbps or Forward Error Correction rate of Gbps • Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit CMU , serial- PRODUCT ORDERING INFORMATION PACKAGE TYPE 196 STBGA OPERATING TEMPERATURE RANGE -40°C to +85°C FIGURE 196 BGA PINOUT OF THE XRT91L82 TOP VIEW A GND RXIP RXIN VDD_CML TXON TXOP VDD_CML TXSCLKON TXSCLKOP VDD_CML REF2CLKP VDD_CML REF1CLKP GND B GND GND VDD_CML VDD_CML VDD_CML GND VDD_CML REF2CLKN GND REF1CLKN GND C AVDD_RX SDEXT SEREFDIS TXCLKO16SELLOCKDET_CDRLOCKDET_CMU TCK TXSCLKOOFFLOOPTM_NOJA VDD_CML CDRLCKREF VDD_CML AVDD_TX / SDI D GND DISRD AVDD_RX PIO_CFG1 /PRBS_LOCK FIFO_RST OVERFLOW PRBS_EN TXSWING / INT DISRDCLK REFREQSEL1 AVDD_TX I2C - SDA / SCLK E RXCAP1P RXCAP1N F / CP_OUT INTERM PIO_CFG0 / VCXO_IN VDD_CMOS GND RESET VDD_CMOS VDD_CMOS PRBS_ERR VDD_CMOS / SDO VDD_CMOS GND VDD_CMOS FEATURES PRODUCT ORDERING INFORMATION FIGURE 196 BGA PINOUT OF THE XRT91L82 TOP 3 TABLE OF CONTENTS I PIN DESCRIPTIONS COMMON CONTROL TRANSMITTER SECTION RECEIVER SERIAL MICROPROCESSOR INTERFACE JTAG FUNCTIONAL DESCRIPTION HARDWARE MODE VS. HOST MODE 16 CLOCK INPUT REFERENCE 16 TABLE 1 REFERENCE FREQUENCY OPTIONS NORMAL MODE/ FEC 16 ALTERNATE CLOCK INPUT REFERENCE HOST MODE ONLY 16 TABLE 2 ALTERNATE REFERENCE FREQUENCY OPTIONS NORMAL MODE/ FEC RATE 17 DATA LATENCY 17 TABLE 3 DATA INGRESS TO DATA EGRESS LATENCY 17 FORWARD ERROR CORRECTION FEC 17 FIGURE SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION 17 PRBS PATTERN GENERATOR AND ANALYZER 17 RECEIVE SECTION RECEIVE SERIAL INPUT 18 FIGURE RECEIVE SERIAL INPUT INTERFACE BLOCK 18 TABLE 4 DIFFERENTIAL CML INPUT SWING PARAMETERS 18 EXTERNAL RECEIVE LOOP FILTER CAPACITORS 19 FIGURE EXTERNAL LOOP FILTER 19 RECEIVE CLOCK AND DATA RECOVERY 19 TABLE 5 CLOCK AND DATA RECOVERY UNIT PERFORMANCE 20 EXTERNAL SIGNAL DETECTION 20 TABLE 6 LOSD DECLARATION POLARITY SETTING 20 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT SIPO 21 FIGURE SIMPLIFIED BLOCK DIAGRAM OF SIPO 21 RECEIVE PARALLEL OUTPUT INTERFACE 21 FIGURE RECEIVE PARALLEL OUTPUT INTERFACE BLOCK 21 RECEIVE PARALLEL INTERFACE LVDS OPERATION 22 FIGURE LVDS EXTERNAL BIASING 22 PARALLEL RECEIVE DATA OUTPUT DISABLE/MUTE UPON LOSD 22 PARALLEL RECEIVE CLOCK OUTPUT DISABLE 22 RECEIVE PARALLEL DATA OUTPUT TIMING 22 FIGURE RECEIVE PARALLEL OUTPUT TIMING 22 TABLE 7 RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS 22 TRANSMIT SECTION TRANSMIT PARALLEL INTERFACE 23 FIGURE TRANSMIT PARALLEL INPUT INTERFACE 23 TRANSMIT PARALLEL DATA INPUT TIMING 24 FIGURE TRANSMIT PARALLEL INPUT TIMING 24 TABLE 8 TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING 24 TABLE 9 TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION 24 TRANSMIT FIFO 24 FIGURE TRANSMIT FIFO AND SYSTEM INTERFACE 25 FIFO CALIBRATION UPON POWER UP 25 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT PISO 25 FIGURE SIMPLIFIED BLOCK DIAGRAM OF PISO 25 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER XRT91L82 CLOCK MULTIPLIER UNIT CMU AND RE-TIMER 26 TABLE 10 CLOCK MULTIPLIER UNIT PERFORMANCE 26 ELECTRICAL CHARACTERISTICS 50 ABSOLUTE MAXIMUM RATINGS 50 ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS 50 POWER AND CURRENT DC ELECTRICAL 50 LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS 51 LVDS LOGIC SIGNAL DC ELECTRICAL 51 LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS 52 ORDERING INFORMATION 53 196 SHRINK THIN BALL GRID ARRAY 53 MM X MM, 53 XRT91L82 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER PIN DESCRIPTIONS XRT91L82 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER COMMON CONTROL NAME LEVEL RESET LVTTL, LVCMOS TYPE I PIO_CFG1 LVTTL, PIO_CFG0 LVCMOS XRES1P XRES1N SE_REF Analog SEREFDIS LVTTL, LVCMOS REF1CLKP LVPECL Diff REF1CLKN E5 Master Reset Input Active low signal. When this pin is pulled "Low" for more than 30ns, the internal registers are set to their default state. See the register description for the default values. This pin is provided with an internal pull-up. D3 Parallel I/O Configuration E3 Selects parallel I/O to be differential LVDS, differential LVPECL, or Single-Ended LVPECL based on table below. PIO_CFG [1:0] 00 10 11 VDD_I/O 3.3V 3.3V 3.3V Input Configuration Output Configuration 3.3V Differential LVPECL 3.3V Differential LVPECL 3.3V Single-Ended LVPECL 3.3V Single-Ended LVPECL ORDERING INFORMATION PACKAGE 196 Shrink Thin Ball Grid Array mm x mm, STBGA OPERATING TEMPERATURE RANGE -40°C to +85°C 196 SHRINK THIN BALL GRID ARRAY MM X MM, STBGA 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A1 Feature/Mark A B C D E F G H J K L M N P A1 corner feature is mfger option Seating Plane A2 A1 A Note The control dimension is in millimeter. SYMBOL A A1 A2 D D1 b e INCHES MILLIMETERS XRT91L82 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER P1.0.0 P1.0.1 November 2004 Preliminary XRT91L82 datasheet. December 2004 Fixed pin-out discrepancies. P1.0.2 January 2005 1.Added CS de-assertion note on section 2.Updated all registers and fixed register 0x02, 0x04, 0x05 microprocessor bit descriptions and modified several functional bit description for active low assertion and default settings. 3.Updated pin descriptions, corrected ’falling edge’ typo error in section to ’rising edge’. 4.Enhanced receive and transmit interface block diagrams and table formats in pin and microprocessor descriptions. 5.Corrected errors in Table 1 Reference Frequency Options. Removed 2.5V I/O support. 6.Remove ’RXSEL’ reference on the RXIP/N pin description. 7.Minor edit in receive section XRT91L82 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER P1.0.3 March 2005 1.Moved microprocessor SDI pin from D10 to pin C10 and SCLK from D4 to pin D12. 2.Moved CP_OUT from pin F14 pin to pin F1 for Host Mode operation only. 3.Moved VCXO_IN from pin E14 to pin E4. 4.Removed IN_TERM in pin E4 to reflect enhanced internal bus termination support. 5.Added RXCAP1P and RXCAP1N/CP_OUT on pins E1 and F1 for external loop filter capacitors. 5.Added XRES1P and XRES1N LVDS biasing external resistors on pins E14 and F14. 6.Renamed RESETB, TXSCLKODIS, FIFO_RST/SCLK, REFREQSEL1, SEREF_EN, RLOOPS/PRBS_CLEAR, DLOOP, TX_SWING, TEST_MODE, PRBS_NOLOCK, RXCLKP/N, RXLCKREF, DISRD, DISRDCLK, LOSEXT pins to RESET, TXSCLKOOFF, FIFO_RST, REFREQSEL1/SCLK, SEREF_DIS, RLOOPS_PRBSCLR, DLOOP, TXSWING, PRBS_EN, PRBS_ERR, RXPCLKOP/N, RXLCKREF, DISRD, DISRDCLK, SDEXT respectively to reflect active low assertion and more precise functionality. 7.Renamed and updated bit description of VDD_3.3 to VDD_IO for 3.3V LVPECL /1.8V LVDS I/O references. 8.Updated STBGA pinout to include above mentioned changes. 9.Retouched 91L82 Block Diagram. 10.Corrected RXDO[15:0]P/N description error from ’updated on rising edge’ to ’updated on falling edge’ of RXPCLKOP/N. 11.Corrected PRBS_EN, FIFO_RST, TXSCLKOOFF description errors 12.Removed unsupported note for transparent mode FIFO operation in section and enhanced and corrected FIFO reset operation description. 13.Corrected Figure 14, “Loop Timing Mode Using an External Cleanup VCXO Host Mode Only 14.Added CMU and CDR performace tables. 15.Added CML input swing characteristics. 16.Added external loop filter and LVDS biasing resistor diagrams. 17.Added Data Latency in section 18.Updated transmit and receive timing diagrams and timing table specifications. 19.Removed all references to limiting amplifier. 20.Significantly enhanced Signal Detection/LOS section description. 21.Change MHz to Mbps to reflect Parallel data I/O and Serial I/O more accurately. Corrected and enhanced PISO and SIPO diagrams. 22.Added JTAG input pin pull-up and pull-down descriptions. 23.Moved FIFO figure from sect to section 24.Enlarged CML output swing figure. 25.Added directional arrows for RXIP/N and TXOP/N. 26.Added place holders for jitter performance charts. 27.Reformatted AC/DC electrical characteristics tables. 28.Rearrange Pin List format and formatted Table Header shading. 29.Added cross-reference for register bits and corrected mispellings and retouched bit descriptions. 30.Updated Microprocessor Register Bits and Descriptions to reflect changes. 31.Changed OC-48 to STS-48 name. XRT91L82 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER P1.0.4 March 2005 1.Renamed RXLCKREF to CDRLCKREF and corrected pin and microprocessor bit description. 2.Reinstated INTERM pin on E4 to support Single-Ended LVPEL in Hardware Mode and added INTERM/VCXO_IN pin description. 3.Renamed AVDD1.8_RX, AVDD1.8_TX, VDD1.8 power and VSS ground pin connections to AVDD_RX, AVDD_TX, VDD_CMOS and GND respectively. 4.Split VDD_IO to VDD_IO and VDD_O and added pin description definition requiring 1.8V potential for VDD_O in LVDS operation. 5.Added ALTFREQSEL to support lower MHz reference clocks, INTERM, and SEREFDIS in Host Mode. 6.Corrected LOOPTM_NOJA pin and microprocessor descripton. 7.Redesigned microprocessor registers. 8.Enhanced Section Electrical Charateristics. 9.Enhanced Figure 1, “Block Diagram of XRT91L82. 10.Updated Figure 2, “196 BGA Pinout of THE XRT91L82 Top View . 11.Corrected typos in pin description section and Figure 5, “External Loop Filter. 12.Enhanced Section "Clock Multiplier Unit CMU and Re-Timer. 13.Updated Figure 14, “Loop Timing Mode Using an External Cleanup VCXO Host Mode Only . P1.0.5 April 2005 1.Changed VDD_O to VDD_IO and removed 1.8V potential requirement for LVDS operation. 2.Added internal termination and biasing notes in pin descriptions. 3.Moved microprocessor INT pin from C5 to pin D10 and SDO from C6 to pin E9. 4.Corrected REFREQSEL1/SCLK pin from D5 to D12. 5.In Host Mode, Added PRBS_LOCK on pin D4. Added PRBS Lock Interrupt Enable, Status, and Detection register bits. Added PRBS inversion capability. 6.Moved PRBS Enable register bit from D3 to D4 in register 0x05h. 7.Changed ALTFREQSEL and TXSWING register bit default values to 8.Corrected Transmit Parallel Interface LVDS Operation section and moved to receive section 9.Updated Figure 14 Loop Timing Mode Using an External Cleanup VCXO. 10.Revised and Updated Electrical Characteristics section NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that a the risk of injury or damage has been minimized b the user assumes all such risks c potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet April Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

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XRT91L82

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

APRIL 2005

The XRT91L82 is a fully integrated SONET/SDH transceiver for OC-48/STM16 applications supporting the use of Forward Error Correction FEC capability. The transceiver includes an on-chip Clock Multiplier Unit CMU , which uses a high frequency PhaseLocked Loop PLL to generate the high-speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery CDR functions by synchronizing its on-chip Voltage Controlled Oscillator VCO to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL system interfaces in both receive and transmit directions. The transmit section includes a 16x9 Elastic Buffer FIFO to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control
of the FIFO_AUTORST register bit can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU and LOCKDET_CDR output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section.
• SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and

Switch/Routers
• DSLAMS
• SONET/SDH Test Equipment
• DWDM Termination Equipment

FIGURE BLOCK DIAGRAM OF XRT91L82

OVERFLOW FIFO_RST

TXDI[15:0]P/N
16 TXPCLKIP/N TXPCLKOP/N TXCLKO16P/N TXCLKO16SEL

STS-48 TRANSCEIVER
16x9 FIFO

RLOOPP

Div by 16

PISO Parallel Input Serial Output

Re-Timer

CMU DLOOP RLOOPS

RXDO[15:0]P/N

RXPCLKOP/N

DISRD DISRDCLK

TDO TDI TCK

TMS TRST

SIPO Serial Input Parallel Output 16

Div by 16

JTAG

Serial Microprocessor

Hardware Control

TXOP/N TXSCLKOP/N

RXIP/N

PFD & Charge Pump

INT RESET

CS SCLK

SDI SDO HOST/HW PIO_CFG [1:0] RLOOPS_PRBSCLR DLOOP LPTIME_NOJA TXSWING TXSCLKOOFF CDRLCKREF SE_REF SEREF_DIS PRBS_EN PRBS_ERR SDEXT POLARITY XRES1P XRES1N LOCKDET_CMU LOCKDET_CDR REF1CLKP/N REF2CLKP/N REFREQSEL1 REFREQSEL0 INTERM/VCXO_IN RXCAP1P RXCAP1N/CPOUT

Exar Corporation 48720 Kato Road, Fremont CA, 94538
• 510 668-7000
• FAX 510 668-7017
•

XRT91L82

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
• / Gbps Transceiver
• Targeted for SONET OC-48/SDH STM-16 Applications
• Selectable full duplex operation between standard rate of Gbps or Forward Error Correction rate of

Gbps
• Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit CMU , serial-
PRODUCT ORDERING INFORMATION

PACKAGE TYPE 196 STBGA

OPERATING TEMPERATURE RANGE -40°C to +85°C

FIGURE 196 BGA PINOUT OF THE XRT91L82 TOP VIEW

A GND

RXIP

RXIN

VDD_CML

TXON

TXOP

VDD_CML TXSCLKON TXSCLKOP VDD_CML REF2CLKP VDD_CML REF1CLKP GND

B GND

GND VDD_CML

VDD_CML

VDD_CML GND

VDD_CML

REF2CLKN GND REF1CLKN GND

C AVDD_RX SDEXT SEREFDIS TXCLKO16SELLOCKDET_CDRLOCKDET_CMU TCK

TXSCLKOOFFLOOPTM_NOJA

VDD_CML CDRLCKREF VDD_CML AVDD_TX
/ SDI

D GND

DISRD AVDD_RX PIO_CFG1
/PRBS_LOCK

FIFO_RST

OVERFLOW

PRBS_EN

TXSWING / INT

DISRDCLK REFREQSEL1

AVDD_TX I2C - SDA / SCLK

E RXCAP1P

RXCAP1N F
/ CP_OUT

INTERM PIO_CFG0
/ VCXO_IN

VDD_CMOS GND

RESET VDD_CMOS

VDD_CMOS

PRBS_ERR VDD_CMOS
/ SDO

VDD_CMOS GND VDD_CMOS
FEATURES PRODUCT ORDERING INFORMATION

FIGURE 196 BGA PINOUT OF THE XRT91L82 TOP 3

TABLE OF CONTENTS I PIN DESCRIPTIONS

COMMON CONTROL TRANSMITTER SECTION RECEIVER SERIAL MICROPROCESSOR INTERFACE JTAG FUNCTIONAL DESCRIPTION

HARDWARE MODE VS. HOST MODE 16 CLOCK INPUT REFERENCE 16

TABLE 1 REFERENCE FREQUENCY OPTIONS NORMAL MODE/ FEC 16

ALTERNATE CLOCK INPUT REFERENCE HOST MODE ONLY 16

TABLE 2 ALTERNATE REFERENCE FREQUENCY OPTIONS NORMAL MODE/ FEC RATE 17

DATA LATENCY 17

TABLE 3 DATA INGRESS TO DATA EGRESS LATENCY 17

FORWARD ERROR CORRECTION FEC 17

FIGURE SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION 17

PRBS PATTERN GENERATOR AND ANALYZER 17 RECEIVE SECTION

RECEIVE SERIAL INPUT 18

FIGURE RECEIVE SERIAL INPUT INTERFACE BLOCK 18 TABLE 4 DIFFERENTIAL CML INPUT SWING PARAMETERS 18

EXTERNAL RECEIVE LOOP FILTER CAPACITORS 19

FIGURE EXTERNAL LOOP FILTER 19

RECEIVE CLOCK AND DATA RECOVERY 19

TABLE 5 CLOCK AND DATA RECOVERY UNIT PERFORMANCE 20

EXTERNAL SIGNAL DETECTION 20

TABLE 6 LOSD DECLARATION POLARITY SETTING 20

RECEIVE SERIAL INPUT TO PARALLEL OUTPUT SIPO 21

FIGURE SIMPLIFIED BLOCK DIAGRAM OF SIPO 21

RECEIVE PARALLEL OUTPUT INTERFACE 21

FIGURE RECEIVE PARALLEL OUTPUT INTERFACE BLOCK 21

RECEIVE PARALLEL INTERFACE LVDS OPERATION 22

FIGURE LVDS EXTERNAL BIASING 22

PARALLEL RECEIVE DATA OUTPUT DISABLE/MUTE UPON LOSD 22 PARALLEL RECEIVE CLOCK OUTPUT DISABLE 22 RECEIVE PARALLEL DATA OUTPUT TIMING 22

FIGURE RECEIVE PARALLEL OUTPUT TIMING 22 TABLE 7 RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS 22

TRANSMIT SECTION TRANSMIT PARALLEL INTERFACE 23

FIGURE TRANSMIT PARALLEL INPUT INTERFACE 23

TRANSMIT PARALLEL DATA INPUT TIMING 24

FIGURE TRANSMIT PARALLEL INPUT TIMING 24 TABLE 8 TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING 24 TABLE 9 TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION 24

TRANSMIT FIFO 24

FIGURE TRANSMIT FIFO AND SYSTEM INTERFACE 25

FIFO CALIBRATION UPON POWER UP 25 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT PISO 25

FIGURE SIMPLIFIED BLOCK DIAGRAM OF PISO 25

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

XRT91L82

CLOCK MULTIPLIER UNIT CMU AND RE-TIMER 26

TABLE 10 CLOCK MULTIPLIER UNIT PERFORMANCE 26
ELECTRICAL CHARACTERISTICS 50 ABSOLUTE MAXIMUM RATINGS 50 ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS 50 POWER AND CURRENT DC ELECTRICAL 50 LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS 51 LVDS LOGIC SIGNAL DC ELECTRICAL 51 LVTTL/LVCMOS SIGNAL DC ELECTRICAL CHARACTERISTICS 52 ORDERING INFORMATION 53 196 SHRINK THIN BALL GRID ARRAY 53 MM X MM, 53

XRT91L82

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

PIN DESCRIPTIONS

XRT91L82

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

COMMON CONTROL

NAME

LEVEL

RESET

LVTTL, LVCMOS

TYPE I

PIO_CFG1

LVTTL,

PIO_CFG0

LVCMOS

XRES1P XRES1N

SE_REF

Analog

SEREFDIS

LVTTL,

LVCMOS

REF1CLKP LVPECL Diff

REF1CLKN

E5 Master Reset Input

Active low signal. When this pin is pulled "Low" for more than 30ns, the internal registers are set to their default state. See the register description for the default values.

This pin is provided with an internal pull-up.

D3 Parallel I/O Configuration

E3 Selects parallel I/O to be differential LVDS, differential LVPECL, or Single-Ended LVPECL based on table below.

PIO_CFG [1:0] 00
10 11

VDD_I/O 3.3V 3.3V 3.3V

Input Configuration

Output Configuration
3.3V Differential LVPECL
3.3V Differential

LVPECL
3.3V Single-Ended

LVPECL
3.3V Single-Ended

LVPECL
ORDERING INFORMATION

PACKAGE 196 Shrink Thin Ball Grid Array mm x mm, STBGA

OPERATING TEMPERATURE RANGE -40°C to +85°C
196 SHRINK THIN BALL GRID ARRAY MM X MM, STBGA
14 13 12 11 10 9 8 7 6 5 4 3 2 1

A1 Feature/Mark

A B C D E F G H J K L M N P

A1 corner feature is mfger option

Seating Plane

A2 A1 A

Note The control dimension is in millimeter.

SYMBOL A A1 A2

D D1 b e

INCHES

MILLIMETERS

XRT91L82

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

P1.0.0 P1.0.1

November 2004 Preliminary XRT91L82 datasheet. December 2004 Fixed pin-out discrepancies.

P1.0.2

January 2005
1.Added CS de-assertion note on section 2.Updated all registers and fixed register 0x02, 0x04, 0x05 microprocessor bit descriptions and modified several functional bit description for active low assertion and default settings. 3.Updated pin descriptions, corrected ’falling edge’ typo error in section to ’rising edge’. 4.Enhanced receive and transmit interface block diagrams and table formats in pin and microprocessor descriptions. 5.Corrected errors in Table 1 Reference Frequency Options. Removed 2.5V I/O support. 6.Remove ’RXSEL’ reference on the RXIP/N pin description. 7.Minor edit in receive section

XRT91L82

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

P1.0.3

March 2005
1.Moved microprocessor SDI pin from D10 to pin C10 and SCLK from D4 to pin D12. 2.Moved CP_OUT from pin F14 pin to pin F1 for Host Mode operation only. 3.Moved VCXO_IN from pin E14 to pin E4. 4.Removed IN_TERM in pin E4 to reflect enhanced internal bus termination support. 5.Added RXCAP1P and RXCAP1N/CP_OUT on pins E1 and F1 for external loop filter capacitors. 5.Added XRES1P and XRES1N LVDS biasing external resistors on pins E14 and F14. 6.Renamed RESETB, TXSCLKODIS, FIFO_RST/SCLK, REFREQSEL1, SEREF_EN, RLOOPS/PRBS_CLEAR, DLOOP, TX_SWING, TEST_MODE, PRBS_NOLOCK, RXCLKP/N, RXLCKREF, DISRD, DISRDCLK, LOSEXT pins to RESET, TXSCLKOOFF, FIFO_RST, REFREQSEL1/SCLK, SEREF_DIS, RLOOPS_PRBSCLR, DLOOP, TXSWING, PRBS_EN, PRBS_ERR, RXPCLKOP/N, RXLCKREF, DISRD, DISRDCLK, SDEXT respectively to reflect active low assertion and more precise functionality. 7.Renamed and updated bit description of VDD_3.3 to VDD_IO for 3.3V LVPECL /1.8V LVDS I/O references. 8.Updated STBGA pinout to include above mentioned changes. 9.Retouched 91L82 Block Diagram. 10.Corrected RXDO[15:0]P/N description error from ’updated on rising edge’ to ’updated on falling edge’ of RXPCLKOP/N. 11.Corrected PRBS_EN, FIFO_RST, TXSCLKOOFF description errors 12.Removed unsupported note for transparent mode FIFO operation in section and enhanced and corrected FIFO reset operation description. 13.Corrected Figure 14, “Loop Timing Mode Using an External Cleanup VCXO Host Mode Only 14.Added CMU and CDR performace tables. 15.Added CML input swing characteristics. 16.Added external loop filter and LVDS biasing resistor diagrams. 17.Added Data Latency in section 18.Updated transmit and receive timing diagrams and timing table specifications. 19.Removed all references to limiting amplifier. 20.Significantly enhanced Signal Detection/LOS section description. 21.Change MHz to Mbps to reflect Parallel data I/O and Serial I/O more accurately. Corrected and enhanced PISO and SIPO diagrams. 22.Added JTAG input pin pull-up and pull-down descriptions. 23.Moved FIFO figure from sect to section 24.Enlarged CML output swing figure. 25.Added directional arrows for RXIP/N and TXOP/N. 26.Added place holders for jitter performance charts. 27.Reformatted AC/DC electrical characteristics tables. 28.Rearrange Pin List format and formatted Table Header shading. 29.Added cross-reference for register bits and corrected mispellings and retouched bit descriptions. 30.Updated Microprocessor Register Bits and Descriptions to reflect changes. 31.Changed OC-48 to STS-48 name.

XRT91L82

GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

P1.0.4

March 2005
1.Renamed RXLCKREF to CDRLCKREF and corrected pin and microprocessor bit description. 2.Reinstated INTERM pin on E4 to support Single-Ended LVPEL in Hardware Mode and added INTERM/VCXO_IN pin description. 3.Renamed AVDD1.8_RX, AVDD1.8_TX, VDD1.8 power and VSS ground pin connections to AVDD_RX, AVDD_TX, VDD_CMOS and GND respectively. 4.Split VDD_IO to VDD_IO and VDD_O and added pin description definition requiring 1.8V potential for VDD_O in LVDS operation. 5.Added ALTFREQSEL to support lower MHz reference clocks, INTERM, and SEREFDIS in Host Mode. 6.Corrected LOOPTM_NOJA pin and microprocessor descripton. 7.Redesigned microprocessor registers. 8.Enhanced Section Electrical Charateristics. 9.Enhanced Figure 1, “Block Diagram of XRT91L82. 10.Updated Figure 2, “196 BGA Pinout of THE XRT91L82 Top View . 11.Corrected typos in pin description section and Figure 5, “External Loop Filter. 12.Enhanced Section "Clock Multiplier Unit CMU and Re-Timer. 13.Updated Figure 14, “Loop Timing Mode Using an External Cleanup VCXO Host Mode Only .

P1.0.5

April 2005
1.Changed VDD_O to VDD_IO and removed 1.8V potential requirement for LVDS operation. 2.Added internal termination and biasing notes in pin descriptions. 3.Moved microprocessor INT pin from C5 to pin D10 and SDO from C6 to pin E9. 4.Corrected REFREQSEL1/SCLK pin from D5 to D12. 5.In Host Mode, Added PRBS_LOCK on pin D4. Added PRBS Lock Interrupt Enable, Status, and Detection register bits. Added PRBS inversion capability. 6.Moved PRBS Enable register bit from D3 to D4 in register 0x05h. 7.Changed ALTFREQSEL and TXSWING register bit default values to 8.Corrected Transmit Parallel Interface LVDS Operation section and moved to receive section 9.Updated Figure 14 Loop Timing Mode Using an External Cleanup VCXO. 10.Revised and Updated Electrical Characteristics section

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Copyright 2005 EXAR Corporation

Datasheet April

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Datasheet ID: XRT91L82IB 512937