EPC9202

EPC9202 Datasheet

DrGaNPLUS Development Board - EPC9202 Quick Start Guide

Part	Datasheet
EPC9202	EPC9202 (pdf)

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DrGaNPLUS Development Board - EPC9202 Quick Start Guide Optimized Half-Bridge Circuit for FETs Single PWM Input Optimized Half Bridge Circuit This development board, measuring 0.36”x contains two enhancement mode field effect transistors FETs arranged in a half bridge configuration with an onboard Texas Instruments LM5113 gate drive and is driven by a single PWM input. The purpose of these development boards is to simplify the evaluation process by optimizing the layout and including all the critical components on a single board that can be easily connected into any existing converter. A complete block diagram of the circuit is given in Figure For more information on EPC’s family of eGaN FETs, please refer to the datasheets available from EPC at The datasheet should be read in conjunction with this quick start guide Table 1 Performance Summary TA = 25°C SYMBOL PARAMETER CONDITIONS UNITS VDD Gate Drive Input Supply Range VIN Bus Input Voltage Range VOUT Switch Node Output Voltage IOUT Switch Node Output Current VPWM PWM Logic Input Voltage Threshold Input ‘High’ Input ‘Low’ Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 200 # * Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to ‘refresh’ high side bootstrap supply voltage. PWM Input Gate Drive Supply Half-Bridge with High Frequency Input Capacitors Logic and LM5113 Dead-time Gate Adjust Driver Figure 1 Block Diagram of Development Board THERMAL CONSIDERATIONS The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C. NOTE. The development board does not have any current or thermal protection on board. TYPICAL PERFORMANCE EPC9202 Figure 2 Typical switch node voltage rising waveform for VIN = 48 V to VOUT =12 V, IOUT =10 A, fsw=300 kHz buck converter E ciency fsw = 300 kHz fsw = 500 kHz 1 2 3 4 5 6 7 8 9 10 11 12 13 Ourput Current A Figure 3 Typical efficiency for VIN=48 V to VOUT = 12 V buck converter with 100 V devices Inductor Coilcraft SER1390-103MLB DESIGN CONSIDERATIONS To improve the electrical and thermal performance of the DrGaNPLUS development board some design considerations are recommended: Large copper planes should be connected to the development board to improve thermal performance as shown in figures 4 through If filled vias are used in the board design, thermal vias should be placed under the device as shown in figure 4 to better distribute heat through buried inner layers. For a design without filled vias, thermal vias should be located outside of the development board as shown in figure Also, for a design without filled vias, the vias to make the VDD connection should be tented and located outside of the VDD pad. To reduce conduction losses, the inductor and output capacitors should be located in close proximity to the development board.

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DrGaNPLUS Development Board - EPC9202 Quick Start Guide

Optimized Half-Bridge Circuit for FETs

Single PWM Input

Optimized Half Bridge Circuit

This development board, measuring 0.36”x contains two enhancement mode field effect transistors FETs arranged in a half bridge configuration with an onboard Texas Instruments LM5113 gate drive and is driven by a single PWM input. The purpose of these development boards is to simplify the evaluation process by optimizing the layout and including all the critical components on a single board that can be easily connected into
any existing converter. A complete block diagram of the circuit is given in Figure

For more information on EPC’s family of eGaN FETs, please refer to the datasheets available from EPC at The datasheet should be read in conjunction with this quick start guide

Table 1 Performance Summary TA = 25°C

SYMBOL PARAMETER

CONDITIONS

UNITS

VDD Gate Drive Input Supply Range VIN Bus Input Voltage Range VOUT Switch Node Output Voltage IOUT Switch Node Output Current

VPWM PWM Logic Input Voltage Threshold

Input ‘High’ Input ‘Low’

Minimum ‘High’ State Input Pulse Width

VPWM rise and fall time < 10ns

Minimum ‘Low’ State Input Pulse Width

VPWM rise and fall time < 10ns
200 #
* Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. # Limited by time needed to ‘refresh’ high side bootstrap supply voltage.

PWM Input

Gate Drive Supply

Half-Bridge with High Frequency Input Capacitors

Logic and LM5113

Dead-time

Gate

Adjust

Driver

Figure 1 Block Diagram of Development Board

THERMAL CONSIDERATIONS The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C. NOTE. The development board does not have any current or thermal protection on board.

TYPICAL PERFORMANCE

EPC9202

Figure 2 Typical switch node voltage rising waveform for VIN = 48 V to VOUT =12 V, IOUT =10 A, fsw=300 kHz buck converter

E ciency
fsw = 300 kHz fsw = 500 kHz
1 2 3 4 5 6 7 8 9 10 11 12 13 Ourput Current A

Figure 3 Typical efficiency for VIN=48 V to VOUT = 12 V buck converter with 100 V devices Inductor Coilcraft SER1390-103MLB

DESIGN CONSIDERATIONS

To improve the electrical and thermal performance of the DrGaNPLUS development board some design considerations are recommended:

Large copper planes should be connected to the development board to improve thermal performance as shown in figures 4 through If filled vias are used in the board design, thermal vias should be placed under the device as shown in figure 4 to better distribute heat through buried inner layers. For a design without filled vias, thermal vias should be located outside of the development board as shown in figure Also, for a design without filled vias, the vias to make the VDD connection should be tented and located outside of the VDD pad.

To reduce conduction losses, the inductor and output capacitors should be located in close proximity to the development board.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived EPC9202 Datasheet file may be downloaded here without warranties.

Datasheet ID: EPC9202 510925