PT7C4502WEX

PT7C4502WEX Datasheet

PT7C4502

Part	Datasheet
PT7C4502WEX	PT7C4502WEX (pdf)

Related Parts	Information
PT7C4502DE	PT7C4502DE
PT7C4502WE	PT7C4502WE
PT7C4502-2WF	PT7C4502-2WF

PDF Datasheet Preview
PT7C4502 PLL Clock Multiplier • Low cost frequency multiplier • Zero ppm multiplication error • Input crystal frequency of 5 - 30 MHz • Input clock frequency of 4 - 50 MHz • Output clock frequencies up to 180 MHz • Period jitter 50ps 100~180MHz • Duty cycle of 45/55% up to 160MHz • Operating voltages of to 5.5V • Tri-state output for board level testing • Die form, Wafer form • Used for crystal oscillator The PT7C4502 is a high performance frequency multiplier, which integrates Analog Phase Lock Loop techniques. The PT7C4502 is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. It is designed to replace crystal oscillators in most electronic systems, clock multiplier and frequency translation. Using Phase-Locked-Loop PLL techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 180 MHz. The complex Logic divider is the ability to generate nine different popular multiplication factors, allowing one chip to output many common frequencies. The device also has an Output Enable pin that tristates the clock output when the OE pin is taken low. This product is intended for clock generation and frequency translation with low output jitter variation in the output period Block Diagram S0 S1 X1/ICLK X2 PLL Clock Synthesis and Control Circuit Crystal Oscillator Output Buffer 2014-09-0002 PT0140-6 09/23/14 PT7C4502 PLL Clock Multiplier Pin/Pad Configuration 1520um 1100um OE X1 -ICLK AVDD DVDD S1 AGND DGND CLK S0 Pin/Pad Description Pin Name Pad Name X1/ICLK X1-ICLK VCC GND OE CLK AVDD DVDD AGND DGND Type I O I O P Description Crystal connection or clock input. Crystal connection. Leave unconnected for clock input. Multiplier select pin Connect to Vcc or float. Multiplier select pin Connect to GND or float. Internal pull-up. Output Enable. Tri-states CLK output when low. Clock output. Analog Power. Digital power. Analog Ground Digital ground. Pad Coordinate File Pad Name X Coordinate Y Coordinate Pad Name X Coordinate Y Coordinate X1-ICLK DVDD Ordering Information Package Code Package PT7C4502DE 350±25µm without coating Die form PT7C4502-2WF 220±20µm with coating Wafer form Note E = Pb-free and Green “-2” shows die thickness is 220±20µm with coating PT7C4502DE die thickness is 350±25µm with coating. Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation  1-800-435-2336  Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 2014-09-0002 PT0140-6 09/23/14

PDF Datasheet Preview

PT7C4502

PLL Clock Multiplier
• Low cost frequency multiplier
• Zero ppm multiplication error
• Input crystal frequency of 5 - 30 MHz
• Input clock frequency of 4 - 50 MHz
• Output clock frequencies up to 180 MHz
• Period jitter 50ps 100~180MHz
• Duty cycle of 45/55% up to 160MHz
• Operating voltages of to 5.5V
• Tri-state output for board level testing
• Die form, Wafer form
• Used for crystal oscillator

The PT7C4502 is a high performance frequency multiplier, which integrates Analog Phase Lock Loop techniques.

The PT7C4502 is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. It is designed to replace crystal oscillators in most electronic systems, clock multiplier and frequency translation.

Using Phase-Locked-Loop PLL techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 180 MHz.

The complex Logic divider is the ability to generate nine different popular multiplication factors, allowing one chip to output many common frequencies.

The device also has an Output Enable pin that tristates the clock output when the OE pin is taken low. This product is intended for clock generation and frequency translation with low output jitter variation in the output period

Block Diagram

S0 S1

X1/ICLK X2

PLL Clock Synthesis and

Control Circuit

Crystal Oscillator

Output Buffer
2014-09-0002

PT0140-6
09/23/14

PT7C4502 PLL Clock Multiplier

Pin/Pad Configuration
1520um
1100um

OE X1 -ICLK

AVDD DVDD

S1 AGND

DGND

CLK S0

Pin/Pad Description

Pin Name Pad Name

X1/ICLK X1-ICLK

VCC GND

OE CLK

AVDD DVDD AGND

DGND

Type I O I O P

Description Crystal connection or clock input. Crystal connection. Leave unconnected for clock input. Multiplier select pin Connect to Vcc or float. Multiplier select pin Connect to GND or float. Internal pull-up. Output Enable. Tri-states CLK output when low. Clock output. Analog Power. Digital power. Analog Ground Digital ground.

Pad Coordinate File

Pad Name X Coordinate Y Coordinate Pad Name X Coordinate Y Coordinate

X1-ICLK

DVDD
Ordering Information

Package Code

Package

PT7C4502DE
350±25µm without coating Die form

PT7C4502-2WF
220±20µm with coating Wafer form

Note E = Pb-free and Green “-2” shows die thickness is 220±20µm with coating PT7C4502DE die thickness is 350±25µm with coating. Adding X Suffix= Tape/Reel

Pericom Semiconductor Corporation  1-800-435-2336 

Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2014-09-0002

PT0140-6
09/23/14

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Datasheet ID: PT7C4502WEX 510119