PI4ULS3V16
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PI4ULS3V16AEX (pdf) |
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PI4ULS3V16ZFE |
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PI4ULS3V16ZFEX |
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PI4ULS3V16AE |
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PI4ULS3V16 1.2V to 3.6V Universal Bidirectional Level Shifter with Automatic Direction Control PI4ULS3V16 is designed for low voltage operation 1.2V to 3.6V Universal bidirectional level shifting with automatic direction control Fast bus speeds up to 180 Mbps for push-pull application Drive Capability 12mA Independent translation of each bit Each supply rail is configurable over supply range ESD Protection exceeds JESD22 - 2000V Human Body Model A114-B -200V Machine Model A115-A Latch-up performance exceeds 100mA per JESD 78 Industrial operation at -40°C to +85°C Package 56-contact plastic 197-mil TQFN Pin Configuration PI4ULS3V16, is a 16-bit dual-octal non-inverting bus transceiver with two separate supply rails A port VCCA and B port VCCB are set to operate at 1.2V to 3.6V. This arrangement permits universal bidirectional translation of differential signal levels over the voltage ranges. The PI4ULS3V16 is designed for asynchronous communication between data buses. Data is transmitted from the A bus to the B bus, or vice versa, without direction control. All AX, and BX are tri-stated when data is coming from both directions at the same time. The output-enable OE input is used to disable outputs so buses are isolated. The control pins xSEL, xOE, TEST_EN and OUT_SEL are supplied by VCCB. To ensure the high impedance state during power- up or power- down, the output-enable OE input should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sinking capability of the driver. Voltage Translation Bus Relay Pin Description Pin Name xSEL xAx xBx TEST_EN OUT_SEL GND VccA,VCCB TSTx 3-State Output Enable Inputs Active Low Outputs Loading Selection Side A Inputs/Outputs Side B Inputs/Outputs Enable Test Mode Output impedance select Ground Power Internal test pins. For normal usage, please tie to ground TQFN-56L Top View 2013-07-0004 PT0483 07/12/13 1 PI4ULS3V16 1.2V to 3.6V Universal Bidirectional Level Shifter with Automatic Direction Control Block Diagram Truth Table Inputs xOE 2SEL 1SEL Outputs Loading 2 CL 50pF CL 30pF CL 20pF CL 10pF Operation Bus B data to Bus A, or Bus A data to Bus B Z Isolation Note H = HIGH Signal Level, L = LOW Signal Level X = Don’t Care or Irrelevant, Z = High Impedance Refer to Figure2for output Loading Chart Test Mode / Output Impedance Select Figure 1 Block Diagram Ordering Information PI4ULS3V16ZFE Note E = Pb-free Adding X Suffix= Tape/Reel Package Code ZF Package Lead free and Green 56-pin TQFN 5x11 Pericom Semiconductor Corporation 1-800-435-2336 Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 2013-07-0004 PT0483 07/12/13 7 |
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