4162122-01

4162122-01 Datasheet

LVDS Add On Board P/N 4162122-01

Part	Datasheet
4162122-01	4162122-01 (pdf)

PDF Datasheet Preview
LVDS Add On Board P/N 4162122-01 The LVDS add-on board P/N 4162122-01 design for dual pixel LVDS panels. It provides jumper setting to select the Data Enable DE signal on transmitter chips. Jumper Settings JP1- Clock phase selection Default 1-2 closed Change this setting to obtain best quality. JP2 - Panel voltage selection 1-3, 2-4 closed 12V panel 3-5, 4-6 closed / 5V panel Default JP3 Enable DE signal on signal or dual LVDS transmitter chip at even pixel side 1-2 closed Enable DE signal on both LVDS transmitter chips U1 & U2 Default - Use for all panels 2-3 closed Enable DE signal on single LVDS transmitter chip U1 Use for all panel except Sharp LQ160E1LG08 and Sharp LQ181E1LW31 Compatible with LVDS board : Old LVDS board Jumper setting on LVDS board P/N 4162122-01 P/N 4162122-00 JP1 2-3 closed JP2 1-3,2-4 closed JP3 1-2 closed P/N 4106886-64 JP1 2-3 closed JP2 3-5,4-6 closed JP3 2-3 closed P/N 4162138-10 JP1 1-2 closed JP2 3-5,4-6 closed JP3 2-3 closed P/N 4162140-10 JP1 1-2 closed JP2 3-5,4-6 closed JP3 1-2 closed Connect with CN5 only Use of connectors Connector CN2 CN3 CN4 CN5 CN6 Connector type Hirose DF11-28DS-2DSA Hirose DF11-32DS-2DSA Hirose DF11-20DF-2DSA Hirose DF14-20P-1.25P Hirose DF14-20P-1.25P Mechanical Drawing : Pin Assignments : CN5 - Hirose DF14-20P-1.25P PIN SYMBOL VLCD Panel power supply VLCD Panel power supply Ground Ground /OUTO0 Negative differential LVDS data O0 OUTO0 Positive differential LVDS data O0 Ground /OUTO1 Negative differential LVDS data O1 OUTO1 Positive differential LVDS data O1 Ground /OUTO2 Negative differential LVDS data O2 OUTO2 Positive differential LVDS data O2 Ground 14 /CLKOUTO Negative LVDS clock O

PDF Datasheet Preview

LVDS Add On Board P/N 4162122-01

The LVDS add-on board P/N 4162122-01 design for dual pixel LVDS panels. It provides jumper setting to select the Data Enable DE signal on transmitter chips.

Jumper Settings JP1- Clock phase selection Default 1-2 closed

Change this setting to obtain best quality.

JP2 - Panel voltage selection 1-3, 2-4 closed 12V panel 3-5, 4-6 closed / 5V panel Default

JP3 Enable DE signal on signal or dual LVDS transmitter chip at even pixel side 1-2 closed Enable DE signal on both LVDS transmitter chips U1 & U2 Default - Use for all panels
2-3 closed Enable DE signal on single LVDS transmitter chip U1 Use for all panel except Sharp LQ160E1LG08 and Sharp LQ181E1LW31

Compatible with LVDS board :

Old LVDS board

Jumper setting on LVDS board P/N 4162122-01

P/N 4162122-00 JP1 2-3 closed JP2 1-3,2-4 closed JP3 1-2 closed

P/N 4106886-64 JP1 2-3 closed JP2 3-5,4-6 closed JP3 2-3 closed

P/N 4162138-10 JP1 1-2 closed JP2 3-5,4-6 closed JP3 2-3 closed

P/N 4162140-10 JP1 1-2 closed JP2 3-5,4-6 closed JP3 1-2 closed

Connect with CN5 only

Use of connectors Connector CN2 CN3 CN4 CN5 CN6

Connector type Hirose DF11-28DS-2DSA Hirose DF11-32DS-2DSA Hirose DF11-20DF-2DSA Hirose DF14-20P-1.25P Hirose DF14-20P-1.25P

Mechanical Drawing :

Pin Assignments :

CN5 - Hirose DF14-20P-1.25P

PIN SYMBOL

VLCD

Panel power supply

VLCD

Panel power supply

Ground

Ground
/OUTO0 Negative differential LVDS data O0

OUTO0

Positive differential LVDS data O0

Ground
/OUTO1 Negative differential LVDS data O1

OUTO1

Positive differential LVDS data O1

Ground
/OUTO2 Negative differential LVDS data O2

OUTO2

Positive differential LVDS data O2

Ground
14 /CLKOUTO

Negative LVDS clock O

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 4162122-01 Datasheet file may be downloaded here without warranties.

Datasheet ID: 4162122-01 509772