CYRF69103-40LFXC

CYRF69103-40LFXC Datasheet

CYRF69103

Part	Datasheet
CYRF69103-40LFXC	CYRF69103-40LFXC (pdf)

PDF Datasheet Preview
CYRF69103 Programmable Radio on Chip Low Power Programmable Radio on Chip Low Power PRoC LP Features • Single Device, Two Functions 8-bit Flash based MCU function and GHz radio transceiver function in a single device. • Flash Based Microcontroller Function M8C based 8-bit CPU, optimized for Human Interface Devices HID applications 256 Bytes of SRAM 8 Kbytes of Flash memory with EEPROM emulation In-System reprogrammable CPU speed up to 12 MHz 16-bit free running timer Low power wakeup timer 12-bit Programmable Interval Timer with interrupts Watchdog timer • Industry leading GHz Radio Transceiver Function Operates in the unlicensed worldwide Industrial, Scientific, and Medical ISM band GHz to GHz DSSS data rates of up to 250 Kbps GFSK data rate of 1 Mbps dBm receive sensitivity Programmable output power up to +4 dBm Auto Transaction Sequencer ATS Framing CRC and Auto ACK Received Signal Strength Indication RSSI Automatic Gain Control AGC • Component Reduction Integrated 1.8V boost converter GPIOs that require no external components Operates off a single crystal • Flexible I/O 2 mA source current on all GPIO pins. Configurable 8 mA or 50 mA/pin current sink on designated pins Each GPIO pin supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output Maskable interrupts on all I/O pins • Operating Voltage from V to V DC • Operating Temperature from 0 to 70 °C • Pb-free 40-pin QFN Package • Advanced Development Tools based on Cypress’s Tools Logic Block Diagram 47µF MOSI SCK nSS 470nF 10 µF RST VBat2 VBat1 VBat0 L/D VReg VCC1 VCC2 VCC3 VDD_MICRO Microcontroller Function P0_1,3,4,7 4 P1_0:2,6:7 5 P2_0:1 2 P1.5/MOSI P1.4/SCK P1.3/nSS GND Xtal RESV GND Vdd RFbias Radio Function IRQ/GPIO MISO/GPIO XOUT/GPIO PACTL/GPIO 12 MHz 470 nF • San Jose, CA 95134-1709 • 408-943-2600 CYRF69103 Contents Applications 3 Functional Description 3 Functional Overview 3 GHz Radio Function 3 Data Transmission Modes 3 Microcontroller Function 3 Backward Compatibility 4 DDR Mode 4 SDR Mode 5 Pinouts 6 Pin Definitions 6 Functional Block Overview 7 GHz Radio 7 Frequency Synthesizer 7 Baseband and Framer 7 Packet Buffers and Radio Configuration Registers 8 Auto Transaction Sequencer ATS 8 Interrupts 9 Clocks 9 GPIO Interface 9 Power On Reset/Low Voltage Detect 9 Timers 9 Power Management 9 Low Noise Amplifier LNA and Received Signal Strength Indication RSSI 11 Receive Spurious Response 11 SPI Interface 11 3-Wire SPI Interface 11 4-Wire SPI Interface 11 SPI Communication and Transactions 12 SPI I/O Voltage References 12 SPI Connects to External Devices 12 CPU Architecture 12 CPU Registers 13 Flags Register 13 Accumulator Register 13 Index Register 14 Stack Pointer Register 14 CPU Program Counter High Register 14 CPU Program Counter Low Register 14 Addressing Modes 15 Source Immediate 15 Source Direct 15 Source Indexed 15 Destination Direct 15 Destination Indexed 16 Destination Direct Source Immediate 16 Destination Indexed Source Immediate 16 Destination Direct Source Direct 16 Source Indirect Post Increment 17 Destination Indirect Post Increment 17 Instruction Set Summary 18 Memory Organization 19 Flash Program Memory Organization 19 Data Memory Organization 20 Flash 20 SROM 20 SROM Function Descriptions 21 Clocking 24 SROM Table Read Description 25 Clock Architecture Description 26 CPU Clock During Sleep Mode 30 Reset 31 Power On Reset 32 Watchdog Timer Reset 32 Sleep Mode 32 Sleep Sequence 32 Low Power in Sleep Mode 33 Wakeup Sequence 33 Radio Function Register Summary 57 Absolute Maximum Ratings 58 DC Characteristics 58 AC Characteristics 60 RF Characteristics 64 Ordering Information 66 Ordering Code Definitions 66 Package Handling 67 Package Diagram 67 Acronyms 69 Document Conventions 69 Units of Measure 69 Document History Page 70 Sales, Solutions, and Legal Information 71 Worldwide Sales and Design Support 71 Products 71 PSoC Solutions 71 Page 2 of 71 CYRF69103 The CYRF69103 PRoC LP is targeted for the following applications: • Wireless HID devices Mice Remote Controls Presenter tools Barcode scanners POS terminal • General purpose wireless applications Industrial applications Home automation White goods Consumer electronics Toys Functional Description PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. Communication between the microcontroller and the radio is through the radio’s SPI interface. Functional Overview The CYRF69103 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69103 is designed to implement low cost wireless systems operating in the worldwide GHz Industrial, Scientific, and Medical ISM frequency band GHz to GHz . GHz Radio Function The SoC contains a GHz 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication RSSI , and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels regulations may limit the use of some of these channels in certain jurisdictions . In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode 1 Mb/s - GFSK the baseband performs Start of Frame SOF , End of Frame EOF detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge ACK handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments. The radio meets the following worldwide regulatory requirements: • Europe ETSI EN 301 489-1 V1.4.1 ETSI EN 300 328-1 V1.3.1 • North America FCC CFR 47 Part 15 • Japan ARIB STD-T66 Data Transmission Modes The radio supports four different data transmission modes: • In GFSK mode, data is transmitted at 1 Mbps, without any DSSS • In 8DR mode, 1 byte is encoded in each PN code symbol transmitted • In DDR mode, 2 bits are encoded in each PN code symbol transmitted • In SDR mode, a single bit is encoded in each PN code symbol transmitted Both 64-chip and 32-chip data PN codes are supported. The four data transmission modes apply to the data after the Start of Packet SOP . In particular, the packet length, data and CRC are all sent in the same mode. Microcontroller Function The MCU function is an 8-bit Flash-programmable microcontroller. The instruction set is optimized specifically for HID and a variety of other embedded applications. The MCU function has up to 8 Kbytes of Flash for user’s code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free Running Timer, and 12-bit Programmable Interrupt Timer. The microcontroller has 15 GPIO pins grouped into multiple ports. With the exception of the four radio function GPIOs, each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port GPIO Port 0 has two dedicated pins that have independent interrupt vectors The microcontroller features an internal oscillator. The PRoC LP includes a Watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1 ms interrupt and a 16-bit free running timer. In addition, the CYRF69103 IC has a Power Management Unit PMU , which enables direct connection of the device to any battery voltage in the range V to V. The PMU conditions the battery voltage to provide the supply voltages required by the device and may supply external devices. Page 3 of 71 CYRF69103 Backward Compatibility The CYRF69103 IC is fully interoperable with the main modes of the first generation Cypress radios namely the CYWUSB6934 -LS and CYWWUSB6935-LR devices. The kbps mode is supported by selecting 32 chip DDR mode. Similarly, the kbps mode is supported by selecting 64 chip SDR mode In this method, a suitably configured CYRF69103 IC device may transmit data to or receive data from a first generation device, or both. Backwards compatibility requires disabling the SOP, length, and CRC16 fields. This section provides the different configurations of the registers and firmware that enable a new generation radio to communicate with a first generation radio. There are two possible modes SDR and DDR mode 8-DR and GFSK modes are not present in the first generation radio . The second generation radio must be initialized using the RadioInitAPI of the LP radio driver and then the following registers’ bits need to be configured to the given Byte values. Essentially, the following deactivates the added features of the second generation radio and takes it down to the level of the first generation radio. The data format, data rates, and the PN codes used are recognizable by the first generation radio. DDR Mode Table DDR Mode Register TX_CFG_ADR RX_CFG_ADR XACT_CFG_ADR FRAMING_CFG_ADR TX_OVERRIDE_ADR RX_OVERRIDE_ADR ANALOG_CTRL_ADR DATA32_THOLD_ADR EOP_CTRL_ADR PREAMBLE_ADR Value 0X16 0X4B 0X05 0X00 0X04 0X14 0X01 0X03 0x01 0xAAAA05 Description 32 chip PN Code, DDR, PA = 6 AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and the RX buffer is configured to receive eight bytes maximum. AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs. All SOP and framing features are disabled. Disable LEN_EN = 0 if EOP is needed. Disable Transmit CRC-16. The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the receiver accepts bad packets that do not match the seed in CRC_seed registers. This helps in communication with the first generation radio that does not have CRC capabilities. Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio. Sets the number of allowed corrupted bits to Sets the number of consecutive symbols for non-correlation to detect end of packet. AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be Page 4 of 71 Ordering Information Package 40-pin Pb-free QFN 6 x 6 mm Punch 40- pin Pb-Free QFN 6 x 6 mm Sawn Ordering Code Definitions CY RF 69103 - 40 LX X C Ordering Part Number CYRF69103-40LFXC CYRF69103-40LTXC Temperature Range C = Commercial Pb-free Package Type LX = LF or LT LF = QFN Punch Type LT = QFN Sawn Type No of pins in package 40-pin Part Number Marketing Code RF = Wireless radio frequency product line Company ID CY = Cypress Page 66 of 71 CYRF69103 Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability. Table Package Handling Parameter TBAKETEMP TBAKETIME Description Bake Temperature Bake Time Unit see package label °C see package label hours Package Diagram Figure 40-pin QFN 6 x 6 x mm LF40A/LY40A x E-Pad Sbcon Punch Type Package Outline SOLDERABLE EXPOSED PAD 001-12917 C Page 67 of 71 CYRF69103 Figure 40-pin QFN 6 x 6 x mm LT40B x E-Pad Sawn Package Outline 001-13190 G Page 68 of 71 CYRF69103 Acronyms Table Acronyms Used in this Document Acronym acknowledge packet received, no errors automatic gain control auto transaction sequencer CMOS complementary metal oxide semiconductor central processing unit EEPROM electrically erasable programmable read-only memory GFSK gaussian frequency-shift keying GPIO general purpose input/output human interface devices input/output industrial, scientific, and medical the same note in the parameter ”RSSI Value for PWRin dBm” . Added Ordering Code Definitions. Updated Package Diagram Added Figure Added Acronyms and Units of Measure. Page 70 of 71 CYRF69103 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 71 of 71 PSoC Designer and Programmable System-on-Chip are trademarks and are registered trademarks of Cypress Semiconductor Corporation. one of its sublicensed Associated Companies conveys a Specification as defined by Philips. As from October 1st, license under the Philips I2C Patent 2006 Philips Semiconductors has a Rights to use these components in an I2C new trade name - NXP Semiconductors. system, provided All products and company names mentioned in this document may be the trademarks of their respective holders.

PDF Datasheet Preview

CYRF69103

Programmable Radio on Chip Low Power

Programmable Radio on Chip Low Power

PRoC LP Features
• Single Device, Two Functions 8-bit Flash based MCU function and GHz radio transceiver function in a single device.
• Flash Based Microcontroller Function M8C based 8-bit CPU, optimized for Human Interface Devices HID applications 256 Bytes of SRAM 8 Kbytes of Flash memory with EEPROM emulation In-System reprogrammable CPU speed up to 12 MHz 16-bit free running timer Low power wakeup timer 12-bit Programmable Interval Timer with interrupts Watchdog timer
• Industry leading GHz Radio Transceiver Function Operates in the unlicensed worldwide Industrial, Scientific, and Medical ISM band GHz to GHz DSSS data rates of up to 250 Kbps GFSK data rate of 1 Mbps dBm receive sensitivity

Programmable output power up to +4 dBm Auto Transaction Sequencer ATS Framing CRC and Auto ACK Received Signal Strength Indication RSSI Automatic Gain Control AGC
• Component Reduction Integrated 1.8V boost converter GPIOs that require no external components Operates off a single crystal
• Flexible I/O 2 mA source current on all GPIO pins. Configurable 8 mA or 50 mA/pin current sink on designated pins Each GPIO pin supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output Maskable interrupts on all I/O pins
• Operating Voltage from V to V DC
• Operating Temperature from 0 to 70 °C
• Pb-free 40-pin QFN Package
• Advanced Development Tools based on Cypress’s Tools

Logic Block Diagram
47µF

MOSI SCK nSS
470nF
10 µF

RST VBat2 VBat1 VBat0 L/D VReg VCC1 VCC2 VCC3

VDD_MICRO

Microcontroller Function

P0_1,3,4,7 4

P1_0:2,6:7 5

P2_0:1 2

P1.5/MOSI P1.4/SCK P1.3/nSS

GND Xtal RESV GND Vdd

RFbias

Radio Function

IRQ/GPIO MISO/GPIO XOUT/GPIO PACTL/GPIO
12 MHz
470 nF
• San Jose, CA 95134-1709
• 408-943-2600

CYRF69103

Contents

Applications 3 Functional Description 3 Functional Overview 3

GHz Radio Function 3 Data Transmission Modes 3 Microcontroller Function 3 Backward Compatibility 4 DDR Mode 4 SDR Mode 5 Pinouts 6 Pin Definitions 6 Functional Block Overview 7 GHz Radio 7 Frequency Synthesizer 7 Baseband and Framer 7 Packet Buffers and Radio Configuration Registers 8 Auto Transaction Sequencer ATS 8 Interrupts 9 Clocks 9 GPIO Interface 9 Power On Reset/Low Voltage Detect 9 Timers 9 Power Management 9 Low Noise Amplifier LNA and Received Signal Strength Indication RSSI 11 Receive Spurious Response 11 SPI Interface 11 3-Wire SPI Interface 11 4-Wire SPI Interface 11 SPI Communication and Transactions 12 SPI I/O Voltage References 12 SPI Connects to External Devices 12 CPU Architecture 12 CPU Registers 13 Flags Register 13 Accumulator Register 13 Index Register 14 Stack Pointer Register 14 CPU Program Counter High Register 14 CPU Program Counter Low Register 14 Addressing Modes 15 Source Immediate 15 Source Direct 15 Source Indexed 15 Destination Direct 15 Destination Indexed 16 Destination Direct Source Immediate 16 Destination Indexed Source Immediate 16 Destination Direct Source Direct 16 Source Indirect Post Increment 17 Destination Indirect Post Increment 17 Instruction Set Summary 18

Memory Organization 19 Flash Program Memory Organization 19 Data Memory Organization 20 Flash 20 SROM 20 SROM Function Descriptions 21

Clocking 24 SROM Table Read Description 25 Clock Architecture Description 26 CPU Clock During Sleep Mode 30

Reset 31 Power On Reset 32 Watchdog Timer Reset 32

Sleep Mode 32 Sleep Sequence 32 Low Power in Sleep Mode 33 Wakeup Sequence 33
Radio Function Register Summary 57 Absolute Maximum Ratings 58 DC Characteristics 58 AC Characteristics 60 RF Characteristics 64 Ordering Information 66
Ordering Code Definitions 66 Package Handling 67 Package Diagram 67 Acronyms 69 Document Conventions 69

Units of Measure 69 Document History Page 70 Sales, Solutions, and Legal Information 71

Worldwide Sales and Design Support 71 Products 71 PSoC Solutions 71

Page 2 of 71

CYRF69103

The CYRF69103 PRoC LP is targeted for the following applications:
• Wireless HID devices Mice Remote Controls Presenter tools Barcode scanners POS terminal
• General purpose wireless applications Industrial applications Home automation White goods Consumer electronics Toys

Functional Description

PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution. Communication between the microcontroller and the radio is through the radio’s SPI interface.

Functional Overview

The CYRF69103 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69103 is designed to implement low cost wireless systems operating in the worldwide GHz Industrial, Scientific, and Medical ISM frequency band GHz to GHz .

GHz Radio Function The SoC contains a GHz 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication RSSI , and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels regulations may limit the use of some of these channels in certain jurisdictions . In DSSS modes the baseband performs DSSS spreading/despreading, while in GFSK Mode 1 Mb/s - GFSK the baseband performs Start of Frame SOF , End of Frame EOF detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge ACK handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, except SDR, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a low moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments.

The radio meets the following worldwide regulatory requirements:
• Europe ETSI EN 301 489-1 V1.4.1 ETSI EN 300 328-1 V1.3.1
• North America FCC CFR 47 Part 15
• Japan ARIB STD-T66

Data Transmission Modes The radio supports four different data transmission modes:
• In GFSK mode, data is transmitted at 1 Mbps, without any DSSS
• In 8DR mode, 1 byte is encoded in each PN code symbol transmitted
• In DDR mode, 2 bits are encoded in each PN code symbol transmitted
• In SDR mode, a single bit is encoded in each PN code symbol transmitted

Both 64-chip and 32-chip data PN codes are supported. The four data transmission modes apply to the data after the Start of Packet SOP . In particular, the packet length, data and CRC are all sent in the same mode.

Microcontroller Function The MCU function is an 8-bit Flash-programmable microcontroller. The instruction set is optimized specifically for HID and a variety of other embedded applications. The MCU function has up to 8 Kbytes of Flash for user’s code and up to 256 bytes of RAM for stack space and user variables. In addition, the MCU function includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free Running Timer, and 12-bit Programmable Interrupt Timer. The microcontroller has 15 GPIO pins grouped into multiple ports. With the exception of the four radio function GPIOs, each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs and CMOS output. Up to two pins support programmable drive strength of up to 50 mA. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port GPIO Port 0 has two dedicated pins that have independent interrupt vectors The microcontroller features an internal oscillator. The PRoC LP includes a Watchdog timer, a vectored interrupt controller, a 12-bit programmable interval timer with configurable 1 ms interrupt and a 16-bit free running timer. In addition, the CYRF69103 IC has a Power Management Unit PMU , which enables direct connection of the device to any battery voltage in the range V to V. The PMU conditions the battery voltage to provide the supply voltages required by the device and may supply external devices.

Page 3 of 71

CYRF69103

Backward Compatibility The CYRF69103 IC is fully interoperable with the main modes of the first generation Cypress radios namely the CYWUSB6934 -LS and CYWWUSB6935-LR devices. The kbps mode is supported by selecting 32 chip DDR mode. Similarly, the kbps mode is supported by selecting 64 chip SDR mode In this method, a suitably configured CYRF69103 IC device may transmit data to or receive data from a first generation device, or both. Backwards compatibility requires disabling the SOP, length, and CRC16 fields.

This section provides the different configurations of the registers and firmware that enable a new generation radio to communicate with a first generation radio. There are two possible modes SDR and DDR mode 8-DR and GFSK modes are not present in the first generation radio . The second generation radio must be initialized using the RadioInitAPI of the LP radio driver and then the following registers’ bits need to be configured to the given Byte values. Essentially, the following deactivates the added features of the second generation radio and takes it down to the level of the first generation radio. The data format, data rates, and the PN codes used are recognizable by the first generation radio.

DDR Mode Table DDR Mode

Register TX_CFG_ADR RX_CFG_ADR

XACT_CFG_ADR

FRAMING_CFG_ADR TX_OVERRIDE_ADR RX_OVERRIDE_ADR

ANALOG_CTRL_ADR

DATA32_THOLD_ADR EOP_CTRL_ADR PREAMBLE_ADR

Value 0X16 0X4B
0X05
0X00 0X04 0X14
0X01
0X03 0x01 0xAAAA05

Description 32 chip PN Code, DDR, PA = 6 AGC is enabled. LNA and attenuator are disabled. Fast turnaround is disabled, the device uses high side receive injection and Hi-Lo is disabled. Overwrite to receive buffer is enabled and the RX buffer is configured to receive eight bytes maximum. AutoACK is disabled. Forcing end state is disabled. The device is configured to transition to Idle mode after a Receive or Transmit. ACK timeout is set to 128 µs. All SOP and framing features are disabled. Disable LEN_EN = 0 if EOP is needed. Disable Transmit CRC-16. The receiver rejects packets with a zero seed. The Rx CRC-16 Checker is disabled and the receiver accepts bad packets that do not match the seed in CRC_seed registers. This helps in communication with the first generation radio that does not have CRC capabilities. Set ALL SLOW. When set, the synthesizer settle time for all channels is the same as the slow channels in the first generation radio. Sets the number of allowed corrupted bits to Sets the number of consecutive symbols for non-correlation to detect end of packet. AAAA are the two preamble bytes. Any other byte can also be written into the preamble register file. Recommended counts of the preamble bytes to be sent must be

Page 4 of 71
Ordering Information

Package 40-pin Pb-free QFN 6 x 6 mm Punch 40- pin Pb-Free QFN 6 x 6 mm Sawn
Ordering Code Definitions

CY RF 69103 - 40 LX X C
Ordering Part Number CYRF69103-40LFXC CYRF69103-40LTXC

Temperature Range C = Commercial Pb-free Package Type LX = LF or LT LF = QFN Punch Type LT = QFN Sawn Type No of pins in package 40-pin Part Number Marketing Code RF = Wireless radio frequency product line Company ID CY = Cypress

Page 66 of 71

CYRF69103

Package Handling

Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may degrade device reliability.

Table Package Handling

Parameter

TBAKETEMP TBAKETIME

Description Bake Temperature Bake Time

Unit
see package label °C
see package label
hours

Package Diagram

Figure 40-pin QFN 6 x 6 x mm LF40A/LY40A x E-Pad Sbcon Punch Type Package Outline

SOLDERABLE EXPOSED PAD
001-12917 *C

Page 67 of 71

CYRF69103

Figure 40-pin QFN 6 x 6 x mm LT40B x E-Pad Sawn Package Outline
001-13190 *G

Page 68 of 71

CYRF69103

Acronyms

Table Acronyms Used in this Document

Acronym
acknowledge packet received, no errors
automatic gain control
auto transaction sequencer

CMOS
complementary metal oxide semiconductor
central processing unit

EEPROM electrically erasable programmable read-only memory

GFSK
gaussian frequency-shift keying

GPIO
general purpose input/output
human interface devices
input/output
industrial, scientific, and medical
the same note in the parameter ”RSSI Value for PWRin dBm” . Added Ordering Code Definitions.

Updated Package Diagram Added Figure

Added Acronyms and Units of Measure.

Page 70 of 71

CYRF69103

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 71 of 71

PSoC Designer and Programmable System-on-Chip are trademarks and are registered trademarks of Cypress Semiconductor Corporation.
one of its sublicensed Associated Companies conveys a Specification as defined by Philips. As from October 1st,
license under the Philips I2C Patent 2006 Philips Semiconductors has a

Rights to use these components in an I2C new trade name - NXP Semiconductors.
system,
provided

All products and company names mentioned in this document may be the trademarks of their respective holders.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYRF69103-40LFXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CYRF69103-40LFXC 508220