CY8C5467AXI-011

CY8C5467AXI-011 Datasheet

5 CY8C54 Family Datasheet

Part	Datasheet
CY8C5467AXI-011	CY8C5467AXI-011 (pdf)

Related Parts	Information
CY8C5468LTI-037	CY8C5468LTI-037
CY8C5467LTI-007	CY8C5467LTI-007
CY8C5466LTI-063	CY8C5466LTI-063
CY8C5466AXI-064	CY8C5466AXI-064
CY8C5468AXI-018	CY8C5468AXI-018

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5 CY8C54 Family Datasheet Programmable System-on-Chip With its unique array of configurable blocks, 5 is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C54 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C54 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C54 family is also a high performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C54 family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C54 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. 32-bit ARM Cortex-M3 CPU core DC to 67 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles, 20 year retention, and multiple security features Up to 64 KB SRAM memory 128 bytes of cache memory 2 KB EEPROM memory, 1 million cycles, and 20 years retention 24-channel DMA with multilayer AHB bus access • Programmable chained descriptors and priorities • High bandwidth 32-bit transfer support Low voltage, ultra low power Operating voltage range V to V 6 mA at 6 MHz 37 mA at 63 MHz Low-power modes including • 2-µA sleep mode • 300-nA hibernate mode with RAM retention Versatile I/O system 46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46x16 segments support from any GPIO[1] V to V I/O interface voltages, up to four domains Maskable, independent IRQ on any pin or port Schmitt-trigger TTL inputs All GPIOs configurable as open drain high/low, pull-up/pull-down, High Z, or strong output 25 mA sink on SIO Digital peripherals 20 to 24 programmable PLD based universal digital blocks UDB Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator Four 16-bit configurable timer, counter, and PWM blocks 67 MHz, 24-bit fixed point digital filter block DFB to implement FIR and IIR filters Library of standard peripherals • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs • SPI, UART, I2C • Many others available in catalog Library of advanced peripherals • Cyclic redundancy check CRC • Pseudo random sequence PRS generator • LIN bus • Quadrature decoder Analog peripherals V VDDA V ±1% internal voltage reference Two SAR ADCs, each 12-bit at 700 ksps Four 8-bit Msps IDACs or 1 Msps VDACs Four comparators with 95 ns response time Four uncommitted opamps with 10 mA drive capability Four configurable multifunction analog blocks. Example configurations are PGA, TIA. Mixer and Sample and hold CapSense support Programming, debug, and trace Serial wire debug SWD and single-wire viewer SWV interfaces Cortex-M3 flash patch and breakpoint FPB block Cortex-M3 data watchpoint and trace DWT generates data trace information Cortex-M3 Instrumentation Trace Macrocell ITM can be used for printf-style debugging DWT and ITM blocks communicate with off-chip debug and trace systems via the SWV interface Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces Precision, programmable clocking 3 to 48 MHz internal oscillator over full temperature and voltage range 4 to 25 MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz kHz watch crystal oscillator Low-power internal oscillator at 1, 33, and 100 kHz Temperature and packaging °C to +85 °C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options Note GPIOs with opamp outputs are not recommended for use with CapSense. • 198 Champion Court San Jose, CA 95134-1709 408-943-2600 5 CY8C54 Family Datasheet Contents Architectural Overview 3 Pinouts 5 Ordering Information 94 Part Numbering Conventions Packaging 96 Acronyms 98 Reference Documents 99 Document Conventions 100 Units of Measure Sales, Solutions, and Legal Information Page 2 of 103 5 CY8C54 Family Datasheet Architectural Overview Introducing the CY8C54 family of ultra low power, flash Programmable System-on-Chip PSoC devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C54 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure Simplified Block Diagram 4 to 25 MHz Optional KHz Optional GPIOs GPIOs GPIOs System Wide Resources Xtal Osc RTC Timer WDT and Wake Clock Tree Usage Example for UDB Sequencer Digital Interconnect Analog Interconnect Digital System Universal Digital Block Array 24 x UDB 8- Bit Quadrature Decoder Timer 16 -Bit PWM UDB 16- Bit PRS UDB UDB I 2C Slave UDB 8- Bit SPI UDB UART UDB 12- Bit SPI UDB 8- Bit Timer Logic Logic UDB 12- Bit PWM Master / Slave 4x Timer Counter PWM FS USB System Bus Ordering Information In addition to the features listed in Table 12-1, every CY8C54 device includes up to 256K flash, 64K SRAM, 2K EEPROM, a precision voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C54 derivatives incorporate device and flash security in user-selectable security levels see the TRM for details. Table CY8C54 Family with ARM Cortex-M3 CPU MCU Core Analog Digital I/O[56] Package Device ID[57] CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADCs DAC Comparators SC/CT Analog Blocks[54] Opamps DFB CapSense UDBs[55] 16-bit Timer/PWM FS USB Total I/O GPIO SIO USBIO CY8C5468AXI-018 CY8C5468LTI-037 CY8C5467AXI-011 CY8C5467LTI-007 CY8C5466AXI-064 CY8C5466LTI-063 67 256 64 2 67 256 64 2 67 128 32 2 67 128 32 2 67 64 16 2 67 64 16 2 2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24 4 70 60 4 46 36 4 70 60 4 46 36 4 70 60 4 46 36 8 2 100-pin TQFP 0x0E112069 8 2 68-pin QFN 0x0E125069 8 2 100-pin TQFP 0x0E10B069 8 2 68-pin QFN 0x0E107069 8 2 100-pin TQFP 0x0E140069 8 2 68-pin QFN 0x0E13F069 Notes Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 30 for more information on how analog blocks can be used. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 30 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 24 for details on the functionality of each of these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Page 94 of 103 5 CY8C54 Family Datasheet Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise. CY8Cabcdefg-xxx a Architecture 3 PSoC 3 5 PSoC 5 b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family c Speed grade 4 40 MHz 6 67 MHz d Flash capacity 5 32 KB 6 64 KB 7 128 KB 8 256 KB ef Package code Two character alphanumeric AX TQFP LT QFN g Temperature range C commercial I industrial A automotive xxx Peripheral set Three character numeric No meaning is associated with these three characters Examples CY8C 5 4 6 8 AX/LT I - x Cypress Prefix 5 PSoC 5 Architecture 5 CY8C54 Family Family Group within Architecture 6 67 MHz Speed Grade 8 256 KB Flash Capacity

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5 CY8C54 Family Datasheet

Programmable System-on-Chip

With its unique array of configurable blocks, 5 is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C54 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples near DC voltages to ultrasonic signals. The CY8C54 family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C54 family is also a high performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C54 family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit Cortex -M3 microprocessor core. Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C54 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
32-bit ARM Cortex-M3 CPU core

DC to 67 MHz operation Flash program memory, up to 256 KB, 100,000 write cycles,
20 year retention, and multiple security features Up to 64 KB SRAM memory 128 bytes of cache memory 2 KB EEPROM memory, 1 million cycles, and 20 years
retention 24-channel DMA with multilayer AHB bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support

Low voltage, ultra low power Operating voltage range V to V 6 mA at 6 MHz 37 mA at 63 MHz Low-power modes including
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention

Versatile I/O system
46 to 70 I/Os 60 GPIOs, 8 SIOs, 2 USBIOs Any GPIO to any digital or analog peripheral routability LCD direct drive from any GPIO, up to 46x16 segments support from any GPIO[1] V to V I/O interface voltages, up to four domains Maskable, independent IRQ on any pin or port Schmitt-trigger TTL inputs All GPIOs configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output 25 mA sink on SIO

Digital peripherals
20 to 24 programmable PLD based universal digital blocks UDB

Full-Speed FS USB 12 Mbps using a 24 MHz external oscillator

Four 16-bit configurable timer, counter, and PWM blocks 67 MHz, 24-bit fixed point digital filter block DFB to
implement FIR and IIR filters

Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, I2C
• Many others available in catalog

Library of advanced peripherals
• Cyclic redundancy check CRC
• Pseudo random sequence PRS generator
• LIN bus
• Quadrature decoder

Analog peripherals V VDDA V ±1% internal voltage reference Two SAR ADCs, each 12-bit at 700 ksps Four 8-bit Msps IDACs or 1 Msps VDACs Four comparators with 95 ns response time Four uncommitted opamps with 10 mA drive capability Four configurable multifunction analog blocks. Example configurations are PGA, TIA. Mixer and Sample and hold CapSense support

Programming, debug, and trace

Serial wire debug SWD and single-wire viewer SWV interfaces

Cortex-M3 flash patch and breakpoint FPB block Cortex-M3 data watchpoint and trace DWT generates data
trace information Cortex-M3 Instrumentation Trace Macrocell ITM can be
used for printf-style debugging DWT and ITM blocks communicate with off-chip debug and
trace systems via the SWV interface Bootloader programming supportable through I2C, SPI,

UART, USB, and other interfaces

Precision, programmable clocking
3 to 48 MHz internal oscillator over full temperature and voltage range
4 to 25 MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz kHz watch crystal oscillator Low-power internal oscillator at 1, 33, and 100 kHz

Temperature and packaging
°C to +85 °C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options

Note GPIOs with opamp outputs are not recommended for use with CapSense.
• 198 Champion Court

San Jose, CA 95134-1709
408-943-2600
5 CY8C54 Family Datasheet

Contents

Architectural Overview 3

Pinouts 5
Ordering Information 94 Part Numbering Conventions

Packaging 96

Acronyms 98

Reference Documents 99

Document Conventions 100 Units of Measure

Sales, Solutions, and Legal Information

Page 2 of 103
5 CY8C54 Family Datasheet

Architectural Overview

Introducing the CY8C54 family of ultra low power, flash Programmable System-on-Chip PSoC devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C54 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure Simplified Block Diagram
4 to 25 MHz Optional

KHz Optional

GPIOs

GPIOs

GPIOs

System Wide Resources

Xtal Osc

RTC Timer

WDT and Wake

Clock Tree Usage Example for UDB

Sequencer

Digital Interconnect

Analog Interconnect

Digital System

Universal Digital Block Array 24 x UDB
8- Bit Quadrature Decoder Timer
16 -Bit PWM UDB
16- Bit PRS UDB

UDB I 2C Slave

UDB 8- Bit SPI

UDB UART

UDB 12- Bit SPI

UDB 8- Bit Timer

Logic

Logic UDB
12- Bit PWM

Master / Slave
4x Timer Counter PWM

FS USB

System Bus
Ordering Information

In addition to the features listed in Table 12-1, every CY8C54 device includes up to 256K flash, 64K SRAM, 2K EEPROM, a precision voltage reference, precision oscillators, flash, DMA, a fixed function I2C, SWD programming and debug, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C54
derivatives incorporate device and flash security in user-selectable security levels see the TRM for details.

Table CY8C54 Family with ARM Cortex-M3 CPU

MCU Core

Analog

Digital

I/O[56]

Package

Device ID[57]

CPU Speed MHz Flash KB SRAM KB EEPROM KB LCD Segment Drive ADCs DAC Comparators SC/CT Analog Blocks[54] Opamps DFB CapSense UDBs[55] 16-bit Timer/PWM FS USB Total I/O GPIO SIO USBIO

CY8C5468AXI-018 CY8C5468LTI-037 CY8C5467AXI-011 CY8C5467LTI-007 CY8C5466AXI-064 CY8C5466LTI-063
67 256 64 2 67 256 64 2 67 128 32 2 67 128 32 2 67 64 16 2 67 64 16 2
2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24 2x12-bit SAR 4 24
4 70 60 4 46 36 4 70 60 4 46 36 4 70 60 4 46 36
8 2 100-pin TQFP 0x0E112069 8 2 68-pin QFN 0x0E125069 8 2 100-pin TQFP 0x0E10B069 8 2 68-pin QFN 0x0E107069 8 2 100-pin TQFP 0x0E140069 8 2 68-pin QFN 0x0E13F069

Notes Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 30 for more information on how analog blocks
can be used. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 30 for more information on how UDBs can be used. The I/O Count includes all types of digital I/O GPIO, SIO, and the two USB I/O. See I/O System and Routing on page 24 for details on the functionality of each of
these types of I/O. The device ID has three major fields. The most significant nibble left digit is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Page 94 of 103
5 CY8C54 Family Datasheet

Part Numbering Conventions PSoC 5 devices follow the part numbering convention described here. All fields are single character alphanumeric 0, 1, 2, 9, A, B, Z unless stated otherwise. CY8Cabcdefg-xxx
a Architecture 3 PSoC 3 5 PSoC 5
b Family group within architecture 2 CY8C52 family 3 CY8C53 family 4 CY8C54 family 5 CY8C55 family
c Speed grade 4 40 MHz 6 67 MHz
d Flash capacity 5 32 KB 6 64 KB 7 128 KB 8 256 KB
ef Package code Two character alphanumeric AX TQFP LT QFN
g Temperature range C commercial I industrial A automotive
xxx Peripheral set Three character numeric No meaning is associated with these three characters

Examples

CY8C 5 4 6 8 AX/LT I - x

Cypress Prefix
5 PSoC 5

Architecture
5 CY8C54 Family

Family Group within Architecture
6 67 MHz

Speed Grade
8 256 KB

Flash Capacity

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Datasheet ID: CY8C5467AXI-011 508170