CY7C68300A-56PVXC

CY7C68300A-56PVXC Datasheet

CY7C68300A

Part	Datasheet
CY7C68300A-56PVXC	CY7C68300A-56PVXC (pdf)

Related Parts	Information
CY7C68300A-56PVC	CY7C68300A-56PVC

PDF Datasheet Preview
CY7C68300A • Complies with USB-IF specifications for USB the USB Mass Storage Class, and the USB Mass Storage Class Bulk-Only Transport Specification • Operates at high 480-Mbps or full 12-Mbps speed • Complies with T13’s ATA/ATAPI-6 Draft Specification • Supports 48-bit addressing for large hard drives • Supports PIO modes 0, 3, 4, and UDMA modes 2, 4 • Uses one external serial EEPROM containing the USB device serial number, vendor and product identification data, and device configuration data • ATA interface IRQ signal support • Support for a single ATA/ATAPI device configured either as master or slave • “ATA-Enable” input signal, which three-states all signals on the ATA interface in order to allow sharing of the bus with another controller e.g., an IEEE-1394 to ATA bridge chip EZ-USB AT2 USB To ATA/ATAPI Bridge • Support for board-level manufacturing test via USB interface • 3.3V operation for self-powered devices • 56-pin SSOP and 56-pin QFN packages. Introduction The CY7C68300A implements a fixed-function bridge between one USB port and one ATA- or ATAPI-based mass storage device port. This bridge adheres to the Mass Storage Class Bulk-Only Transport Specification and is intended for self-powered devices. The USB port of the CY7C68300A is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the CY7C68300A and receives status and data from the CY7C68300A using standard USB protocol. The ATA/ATAPI port of the CY7C68300A is connected to a mass storage device. A 4-Kbyte buffer maximizes ATA/ATAPI SCL SDA I2C-Compatible Bus Controller RESET 24 MHz XTAL VBUS D+ D- PLL USB XCVR AT2 Internal Logic ATA_EN ATA Interf ace 3-state ATA Interf ace ControlSignals Control ATA Interf ace 16 Bit ATA Data Logic CY SmartUSB FS/HSEngine 4kBy teFIFO Data Figure Block Diagram • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C68300A data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0, 3, and 4, and Ultra DMA modes 2 and The device initialization process is configurable, enabling the CY7C68300A to initialize ATA/ATAPI devices without software intervention. Pin Assignments Pin Diagram 1 DD13 2 DD14 3 DD15 4 GND 5 NC 6 Vcc 7 GND 8 IORDY 9 DMARQ 10 AVcc 11 XTALOUT 12 XTALIN 13 AGND 14 Vcc 15 DPLUS 16 DMINUS 17 GND 18 Vcc 19 GND 20 PU10K 21 RESERVED 22 SCL 23 SDA 24 Vcc 25 DD0 26 DD1 27 DD2 28 DD3 DD12 56 Ordering Information Package Type CY7C68300A-56PVC 56-pin SSOP CY7C68300A-56LFC 56-pin QFN CY7C68300A-56PVXC 56-pin Lead Pb -free SSOP CY7C68300A-56LFXC 56-pin Lead Pb -Free QFN CY4615A EZ-USB AT2 Reference Design Kit Note If an alternate clock source is input on XTALIN it must be supplied with standard 3.3V signaling characteristics and XTALOUT must be left floating. Page 19 of 21 Package Diagrams CY7C68300A DIMENSIONS IN INCHES MIN. MAX. SEATING PLANE GAUGE PLANE 0° -8° Figure 56-lead Shrunk Small Outline Package 056 56-Lead QFN 8 x 8 MM LF56A 51-85062-C TOP VIEW DIA. SIDE VIEW MAX. MAX. C MAX. REF. 0° -12° C SEATING PLANE BOTTOM VIEW PIN1 ID E-PAD PAD SIZE VARY BY DEVICE TYPE 51-85144-D Figure 56-lead Quad Flatpack No Lead 8 x 8 mm LF56A Disclaimers, Trademarks, and Copyrights Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EZ-USB AT2 is a trademark, and EZ-USB is a registered trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Page 20 of 21 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress CY7C68300A Document History Page Description Title CY7C68300A EZ-USB AT2 USB to ATA/ATAPI Bridge Document Number 38-08031 ECN NO. Issue Date Orig. of Change 285992 SEE ECN GIR Corrected existing ordering part numbers. Added lead-free ordering part numbers Page 21 of 21

PDF Datasheet Preview

CY7C68300A
• Complies with USB-IF specifications for USB the USB Mass Storage Class, and the USB Mass Storage Class Bulk-Only Transport Specification
• Operates at high 480-Mbps or full 12-Mbps speed
• Complies with T13’s ATA/ATAPI-6 Draft Specification
• Supports 48-bit addressing for large hard drives
• Supports PIO modes 0, 3, 4, and UDMA modes 2, 4
• Uses one external serial EEPROM containing the USB device serial number, vendor and product identification data, and device configuration data
• ATA interface IRQ signal support
• Support for a single ATA/ATAPI device configured either as master or slave
• “ATA-Enable” input signal, which three-states all signals on the ATA interface in order to allow sharing of the bus with another controller e.g., an IEEE-1394 to ATA bridge chip

EZ-USB AT2 USB To ATA/ATAPI Bridge
• Support for board-level manufacturing test via USB interface
• 3.3V operation for self-powered devices
• 56-pin SSOP and 56-pin QFN packages.

Introduction

The CY7C68300A implements a fixed-function bridge between one USB port and one ATA- or ATAPI-based mass storage device port. This bridge adheres to the Mass Storage Class Bulk-Only Transport Specification and is intended for self-powered devices.

The USB port of the CY7C68300A is connected to a host computer directly or via the downstream port of a USB hub. Host software issues commands and data to the CY7C68300A and receives status and data from the CY7C68300A using standard USB protocol.

The ATA/ATAPI port of the CY7C68300A is connected to a mass storage device. A 4-Kbyte buffer maximizes ATA/ATAPI

SCL SDA

I2C-Compatible Bus Controller

RESET
24 MHz XTAL

VBUS D+ D-

PLL USB XCVR

AT2 Internal Logic

ATA_EN ATA Interf ace 3-state

ATA Interf ace ControlSignals

Control ATA

Interf ace 16 Bit ATA Data Logic

CY SmartUSB FS/HSEngine
4kBy teFIFO

Data

Figure Block Diagram
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C68300A
data transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0, 3, and 4, and Ultra DMA modes 2 and

The device initialization process is configurable, enabling the CY7C68300A to initialize ATA/ATAPI devices without software intervention.

Pin Assignments

Pin Diagram
1 DD13 2 DD14 3 DD15 4 GND 5 NC 6 Vcc 7 GND 8 IORDY 9 DMARQ 10 AVcc 11 XTALOUT 12 XTALIN 13 AGND 14 Vcc 15 DPLUS 16 DMINUS 17 GND 18 Vcc 19 GND 20 PU10K 21 RESERVED 22 SCL 23 SDA 24 Vcc 25 DD0 26 DD1 27 DD2 28 DD3

DD12 56
Ordering Information

Package Type

CY7C68300A-56PVC 56-pin SSOP

CY7C68300A-56LFC 56-pin QFN

CY7C68300A-56PVXC 56-pin Lead Pb -free SSOP

CY7C68300A-56LFXC 56-pin Lead Pb -Free QFN

CY4615A

EZ-USB AT2 Reference Design Kit

Note If an alternate clock source is input on XTALIN it must be supplied with standard 3.3V signaling characteristics and XTALOUT must be left floating.

Page 19 of 21

Package Diagrams

CY7C68300A

DIMENSIONS IN INCHES MIN.

MAX.

SEATING PLANE

GAUGE PLANE
0° -8°

Figure 56-lead Shrunk Small Outline Package 056 56-Lead QFN 8 x 8 MM LF56A
51-85062-*C

TOP VIEW

DIA.

SIDE VIEW MAX. MAX.

C MAX. REF.
0° -12° C

SEATING PLANE

BOTTOM VIEW

PIN1 ID

E-PAD

PAD SIZE VARY BY DEVICE TYPE
51-85144-*D

Figure 56-lead Quad Flatpack No Lead 8 x 8 mm LF56A

Disclaimers, Trademarks, and Copyrights

Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EZ-USB AT2 is a trademark, and EZ-USB is a registered trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 20 of 21

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

CY7C68300A

Document History Page

Description Title CY7C68300A EZ-USB AT2 USB to ATA/ATAPI Bridge Document Number 38-08031

ECN NO.

Issue Date

Orig. of Change
285992 SEE ECN GIR Corrected existing ordering part numbers.
Added lead-free ordering part numbers

Page 21 of 21

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C68300A-56PVXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C68300A-56PVXC 508143